Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

Abstract: Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

Abstract: Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

Abstract: A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

Abstract: A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

Abstract: Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

Abstract: A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

Abstract: A carry circuit having a power-save mode and a method for reducing power consumption of an integrated circuit are described. A power-save input is selected for control select signaling. A voltage level input is selected as an initial carry input. The initial carry input is propagated through a carry stage responsive to the carry input and the control select signaling. The carry stage is placed in a first non-switching steady state mode responsive to the propagating of the initial carry input through the carry stage.