Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: The invention relates to an integrated circuit memory unit comprising: a memory cell, a switched bulk DC voltage source and a plurality of wordline-controlled transistors. Each of wordline-controlled transistors has a bulk connected to the switched bulk DC voltage source. When the data bit is read from the memory cell or the data bit is written into the memory cell, the bulks of the wordline-controlled transistors are switched to a first voltage level from the switched bulk DC voltage source so as to increase the drain current and obtain faster operation speed. When in an idle mode, the bulks of the wordline-controlled transistors are switched to a second voltage level from the switched bulk DC voltage source so as to obtain higher threshold voltage and decrease the leakage current.