Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.

Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/2 and M is greater than K/2.

Abstract: A super resolution (SR) image generating device includes a receiving circuit, a first configurable basic block pool circuit, a first shuffle circuit, a second configurable basic block pool circuit, and a second shuffle circuit. The receiving circuit is arranged to receive an input image. The first configurable basic block pool circuit is arranged to configure multiple first basic blocks according to the input image for performing convolution operations, to generate multiple first operation results. The first shuffle circuit is arranged to shuffle the multiple first operation results to generate a first SR output image. The second configurable basic block pool circuit is arranged to configure multiple second basic blocks according to the input image for performing convolution operations, to generate multiple second operation results. The second shuffle circuit is arranged to shuffle the multiple second operation results to generate a second SR output image.

Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

Abstract: A method for training a super-resolution model, a super-resolution method, and a system are provided, and the super-resolution method and the system are implemented through an AI super-resolution model that is trained by the method. In the method, an input image is provided, and a magnification ratio and an image quality threshold are set. Pixel values of the input image are retrieved, and image features of the input image are extracted. Multiple channel images are obtained through a super-resolution model based on the image features and the magnification ratio. Phase information can be obtained according to the magnification ratio and positions of output pixels, and the phase information is used to obtain masks mapping to the channel images. Therefore, an output image can be reshuffled. After a comparison with the image quality threshold, model parameters of the output image can be assessed for training the AI super-resolution model.

Abstract: A baffle structure, with a variable position installed on the cabinet. The baffle structure comprises a board, adjusting element, and fixing element. A first slot is defined on the board, and the first slot extends along the first direction. The adjusting element is slidably arranged in the first slot, and partially extends outside the first slot until it fits with a main body of the cabinet. The board is positioned relative to the main body on the second direction. The fixing element is set on the board and configured to position the board relative to the main body on the third direction. The second direction is perpendicular to first direction, and the third direction is perpendicular to the first direction and the second direction.

Abstract: The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

Abstract: A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate. The method further includes using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Abstract: Disclosed are an image tuning device and an image tuning method. The image tuning method includes the following steps: dividing an image area into a plurality of blocks for executing brightness adjustment individually, in which the blocks include a target block and at least one neighboring block; receiving pixel data of the target block to calculate a target block brightness value; receiving pixel data of the at least one neighboring block to calculate at least one neighboring block brightness value; calculating a calculated brightness value of a target pixel within the target block according to the target block brightness value and the at least one neighboring block brightness value; and generating an adjusted brightness value of the target pixel by adjusting an original brightness value of the target pixel according to the calculated brightness value.

Abstract: A video processing method for a video processing circuit includes receiving a first video source corresponding to a first pixel rate and a second video source corresponding to a second pixel rate, wherein a processing data rate of a video processing path is greater than or equal to a sum of the first pixel rate and the second pixel rate, and using the processing data rate to sequentially perform an image processing to a first image of the first video source and a second image of the second video source corresponding to the same display time, to generate a first processed image and a second processed image.

Abstract: Disclosed are an image tuning device and an image tuning method. The image tuning method includes the following steps: dividing an image area into a plurality of blocks for executing brightness adjustment individually, in which the blocks include a target block and at least one neighboring block; receiving pixel data of the target block to calculate a target block brightness value; receiving pixel data of the at least one neighboring block to calculate at least one neighboring block brightness value; calculating a calculated brightness value of a target pixel within the target block according to the target block brightness value and the at least one neighboring block brightness value; and generating an adjusted brightness value of the target pixel by adjusting an original brightness value of the target pixel according to the calculated brightness value.

Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

Abstract: A key module (10) includes a light guiding board (14), a flexible key board (12) disposed on the light guiding board, and a plurality of metallic elastic sheets (164). Each of the metallic elastic sheets is disposed on the light guiding board and located opposite to the flexible key board. The light guiding board deforms when the flexible key board is pressed thereby causing the metallic elastic sheet corresponding to a location of the flexible key board being pressed to be deformed.

Abstract: An ink jet cartridge. The ink jet cartridge includes a housing having a chamber, an absorbing member installed in the chamber, and a cover having a first opening therethrough and a protrusion formed on the cover surface toward the absorbing member around the first opening.

Abstract: A deblocking filtering method used on video encoding/decoding includes: sequentially reading the subblocks adjacent to a vertical edge according to a deblocking direction, and performing a deblocking process on the vertical edge; performing a transposition on the pixel data of a current subblock; performing the deblocking process on a parallel edge of the current subblock, and outputting the pixel data of another subblock adjacent to the parallel edge after transposition; sequentially storing a plurality of current subblocks; transposing and outputting the pixel data of the plurality of current subblocks after completion of the deblocking of the current macroblock.

Abstract: An ink jet cartridge. The ink jet cartridge includes a housing having a chamber, an absorbing member installed in the chamber, and a cover having a first opening therethrough and a protrusion formed on the cover surface toward the absorbing member around the first opening.