Patents by Inventor TIEN-KUO LIN

TIEN-KUO LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF
    Publication number: 20240012974
    Abstract: An integrated circuit includes a functional circuit and a first power switch chain. The first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power source and the functional circuit. The first power switch chain is configured to receive a first control signal, and the first control signal is configured to turn on or turn off the first power switch circuit and the second power switch circuit. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.
    Type: Application
    Filed: July 2, 2023
    Publication date: January 11, 2024
    Inventor: Tien-Kuo LIN
  • Method for integrated circuit layout
    Patent number: 11030379
    Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 8, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tien-Kuo Lin, Li-Yi Lin, Yun-Chih Chang
  • Method for integrated circuit layout
    Publication number: 20210034808
    Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 4, 2021
    Inventors: TIEN-KUO LIN, LI-YI LIN, YUN-CHIH CHANG