Abstract: A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a VCC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the VCC power supply to ensure the memory cell array is properly erased.

Abstract: A novel flash memory array has an array of memory cells with each memory cell being of a floating gate memory transistor with a plurality of terminals. The memory cells are arranged in a plurality of rows and a plurality of columns, with a word line connecting the memory cells in the same row. A row decoder is positioned adjacent one side of the memory array and is connected to the plurality of word lines for receiving an address signal and for supplying a low voltage signal. A plurality of programming lines are connected to the plurality of rows of memory cells of the array with a programming line connected to the memory cells in the same row. The plurality of programming lines are collinear with but spaced apart from the plurality of word lines and extending only to the row decoder.

Abstract: A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a V.sub.CC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the V.sub.CC power supply to ensure the memory cell array is properly erased.