Abstract: A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.

Abstract: An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Abstract: A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.

Abstract: An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Abstract: An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Abstract: One example includes a voltage clamp circuit. The voltage clamp circuit includes a comparator loop circuit. The comparator loop circuit includes a comparator configured to compare an input voltage provided at an input node with a clamping voltage. The comparator loop circuit also includes a transistor network interconnecting a voltage rail and the input node. The comparator can be configured to activate the transistor network to set the input voltage to be approximately equal to the clamping voltage in response to the input voltage exceeding the corresponding clamping voltage.

Abstract: An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.

Abstract: An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage.