Abstract: A liveness detection method includes: obtaining multiple first feature points and multiple second feature points according to a first image, a second image, and a feature point process, wherein the first feature points include two first fixed feature points and at least one first variable feature point, and the second feature points include two second fixed feature points and at least one second variable point; obtaining a first transform function according to the first fixed feature points and the second fixed feature points; obtaining at least one check feature point according to the first transform function and the first variable feature point(s); and determining whether the second image is a spoofing image according to the check feature point(s) and the second variable point(s).

Abstract: A license plate recognition system includes an image capturing module, a license plate detection module, a segment extraction module, a character classification module, and a character recognition module. The image capturing module is for capturing an image. The license plate detection module is for receiving the image and to identify a license plate in the image. The segment extraction module is for extracting a sequence of character segments on the license plate. The character classification module is for computing a probability of each possible character in each character segment. The character recognition module is for identifying permissible characters for the each character segment according to a syntax of the sequence of character segments, and to identify a character having a highest probability among the permissible characters as a selected character for the each character segment.

Abstract: A license plate recognition system includes an image capturing module, a license plate detection module, a segment extraction module, a character classification module, and a character recognition module. The image capturing module is for capturing an image. The license plate detection module is for receiving the image and to identify a license plate in the image. The segment extraction module is for extracting a sequence of character segments on the license plate. The character classification module is for computing a probability of each possible character in each character segment. The character recognition module is for identifying permissible characters for the each character segment according to a syntax of the sequence of character segments, and to identify a character having a highest probability among the permissible characters as a selected character for the each character segment.

Abstract: An object localization system including an object detection module configured to detect an object in a current frame with reference to a preceded frame, and an object localization module configured to identify a location of the object according to the segment. The object detection module includes a difference module for computing differences between the preceded frame and the current frame at a same location to generate a difference frame, a selected block detection module for identifying a selected block of the difference frame according to a predetermined minimum difference, a segment generation module for generating a segment of the current frame.

Abstract: An object localization system including an object detection module configured to detect an object in a current frame with reference to a preceded frame, and an object localization module configured to identify a location of the object according to the segment. The object detection module includes a difference module for computing differences between the preceded frame and the current frame at a same location to generate a difference frame, a selected block detection module for identifying a selected block of the difference frame according to a predetermined minimum difference, a segment generation module for generating a segment of the current frame.

Abstract: The present disclosure discloses a video pipeline comprising: a video processor operable to output at least an image processing parameter and at least an encoding parameter according to one or both of at least one parameter and at least one instruction from a domain outside the video pipeline; an image signal processor operable to turn image raw data into lower resolution video data and video data according to the at least one image processing parameter; a streaming conversion circuit operable to convert the video data into converted data; and an encoder operable to encode video data and encode the converted data according to the at least one encoding parameter.

Abstract: The present disclosure discloses an image frame processing method for processing a plurality of input image frames with an image processing device. An embodiment of the method comprises: receiving a plurality of input image frames; and processing the plurality of input image frames to produce a first number of first output image frames and a second number of second output image frames, in which the resolution of the first output image frames is higher than the resolution of the second output image frames and the first number is less than the second number, wherein a first frame of the first output image frames and a second frame of the second output image frames are derived from the same one of the plurality of input image frames.

Abstract: The present disclosure discloses an image frame processing method for processing a plurality of input image frames with an image processing device. An embodiment of the method comprises: receiving a plurality of input image frames; and processing the plurality of input image frames to produce a first number of first output image frames and a second number of second output image frames, in which the resolution of the first output image frames is higher than the resolution of the second output image frames and the first number is less than the second number, wherein a first frame of the first output image frames and a second frame of the second output image frames are derived from the same one of the plurality of input image frames.

Abstract: The present disclosure discloses a video pipeline comprising: a video processor operable to output at least an image processing parameter and at least an encoding parameter according to one or both of at least one parameter and at least one instruction from a domain outside the video pipeline; an image signal processor operable to turn image raw data into lower resolution video data and video data according to the at least one image processing parameter; a streaming conversion circuit operable to convert the video data into converted data; and an encoder operable to encode video data and encode the converted data according to the at least one encoding parameter.

Abstract: Provided is a decoding device which can perform video decoding in a real time with a sophisticated video specification requiring a frequent access to an external memory. A video decoding device (100) includes a hardware video decoder (115) which executes decoding of a pixel coefficient and write of a reconfigured picture into an external memory (110). A hardware video decoder (115) includes: a hardware engine pipeline (201) formed by a plurality of hardware engines requiring a DMA read access or a DMA write access to the external memory (110) or both of the accesses; and a hardware video decoder DMA controller (200) which adjusts all the DMA accesses from the hardware engines to one DMA channel or a plurality of DMA channels to a DMA controller (111).

Abstract: Provided is a video encoding and decoding device which can use limited memory resources to maximize system performance. After a direct memory access means (160) of a motion-compensation device (101) generates a DMA request after an interpolation complete was received from an interpolation means (180), and a DMA ACK was received from a memory access arbitration means (110), a video encoding and decoding device (100) receives a plurality of DMA input data in accordance with the maximum DMA burst constraint and the block buffer size constraint, and generates the block memory address for storing the reference pixel data in a variable size block buffer (170) in accordance with the decoding parameters, the calculation process level Lc, the maximum DMA burst constraint, and the block buffer size constraint.

Abstract: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.

Abstract: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.