Patents by Inventor TIEN-SHAO CHUANG

TIEN-SHAO CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149039
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Patent number: 11251069
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Publication number: 20200411363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Patent number: 10790184
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Publication number: 20200105612
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Publication number: 20150129022
    Abstract: A back contact solar cell includes a solar cell substrate, an intrinsic layer, a second conductive type semiconductor layer and an electrode layer. The solar cell substrate includes a substrate body doped with a first conductive type semiconductor and a plurality of first conductive type semiconductor doped regions. The first conductive type semiconductor doped region is formed on a back side of the substrate body. The intrinsic layer is formed on the back side, and includes a plurality of first openings to expose the first conductive type semiconductor doped regions. The second conductive type semiconductor layer is deposited on the intrinsic layer, and includes a plurality of second openings correspond the first openings. The electrode layer includes a plurality of first electrode regions and a second electrode region. The first electrode regions are disposed on the first conductive type semiconductor doped regions.
    Type: Application
    Filed: June 24, 2014
    Publication date: May 14, 2015
    Inventors: Chorngjye HUANG, Feng-Yu YANG, Shan-Chuang PEI, Ching-Chun YEH, Tien-Shao CHUANG
  • Publication number: 20150096612
    Abstract: A back-contact solar cell and manufacturing method thereof includes steps of providing a substrate, forming a first conductive doping region and a second conductive doping region on the substrate, forming a passivation layer on the substrate to cover the first conductive doping region and the second conductive doping region, distantly disposing a plurality of first electrode paste clusters on the passivation layer, in which each first electrode paste cluster corresponds to the first conductive doping region and the second conductive doping region and includes a metal component and a glass component, enclosing the first electrode paste cluster by a plurality of second electrode pastes, and heating at least the first electrode paste clusters to an predetermined temperature so that the metal component, the metal component and the passivation layer contacted by the first electrode paste clusters forms a plurality of contacting regions.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 9, 2015
    Inventors: SHAO-CHIN TSENG, TIEN-SHAO CHUANG, KUN-CHIH LIN