Abstract: The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The semiconductor layer located outside the source area, the drain area and the fillister will be removed. And then, the stack structure is then removed. Therefore, the semiconductor layer filled inside the fillister will be exposed to be as a channel. A gate oxide layer is formed to cover the channel, and a gate layer is then formed on the gate oxide layer.

Abstract: A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well.

Abstract: A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well.

Abstract: The present invention relates to a novel process for removing sidewall residue after dry-etching process. Conventionally, after dry-etching, photoresist and sidewall residues are removed by ozone ashing and hot sulfuric acid. Normally, they are hard to be removed completely. It was found in the present invention that the addition of fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in sulfuric acid results in complete removal of photoresist and sidewall residue without the need for stripper. The process is simple and does not affect the original procedures or the other films on the substrate. The present invention also relates to a novel solution for removing sidewall residue after dry-etching, which comprises sulfuric acid and a fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in the range of from 10:1 to 1000:1 by weight.

Abstract: A solution for cleaning silicon semiconductors or silicon oxides comprising H2O2, NH4OH and at least one component A selected from the group consisting of fluoro-containing compounds and other ammonium salts than NH4OH, wherein the weight ratio of H2O2 to H2O is between 1:5 and 1:50, the weight ratio of NH4OH to H2O is between 1:5 and 1:50, and the molar ratio of component A to NH4OH is between 1:10 and 1:5000 is disclosed. The solution can achieve the efficacy equivalent to that of the conventional RCA two-step cleaning solution within a shorter time by one step and effectively remove contaminants such as organics, dust and metals from the surfaces of silicon semiconductors and silicon oxides without using strong acids such as HCl and H2SO4.

Abstract: The present invention discloses a method of oxidizing a nitride film on a conductive substrate comprising the following steps. First, a conductive substrate is provided, and a nitride film is formed on the main surface of the conductive substrate by performing film deposition process or directly nitridating the surface region of the conductive substrate. Then, a local electrode terminal (such as a conductive probe of a scanning-probe microscope) is provided, and a strong electric field is locally generated between the electrode terminal and the conductive substrate in an oxidizing environment, wherein the strong electric field passes through the nitride film, thereby oxidizing the nitride film region passed by the electric field. The method of oxidizing a nitride film according to the present invention can be applied to define patterns on a nitride film, to record information as memory media, and to form growth templates for the use in chemical selective formation processes.

Abstract: A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process.

Abstract: The present invention is to develop a proper new process for deep submicron PMOSFET. The characteristic of this process is using Si:Ge:B layer to deposit on the poly-Si film, then go through oxidation or diffusion method to diffuse the boron ion into the poly-Si gate in order to form p-type poly-Si gate. This layer can be etched selectively after spacer etching and reserve a concave gate structure. Thus, it can combine with selective W-CVD to form an excellent p-type poly-Si PMOSFET.