Patents by Inventor Tien-Shun Chang

Tien-Shun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055300
    Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ting CHANG, Kuo-Ju CHEN, Tien-Shun CHANG, Su-Hao LIU, Huicheng CHANG
  • Publication number: 20230387251
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20230377913
    Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230268423
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition having a second etch rate, the second etch rate being different from the first etch rate; etching a first recess in the first region of the substrate having the second composition and a second recess in the second region having the first composition; and epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 24, 2023
    Inventors: Tien-Shun Chang, Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230261055
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 11670683
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 11640986
    Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
  • Publication number: 20230016619
    Abstract: A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.
    Type: Application
    Filed: March 2, 2022
    Publication date: January 19, 2023
    Inventors: Tien-Shun Chang, Yu-Kang Liu, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220359301
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11450757
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20220262644
    Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11367621
    Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220028707
    Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210391182
    Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210375687
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210367038
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Publication number: 20210328044
    Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
  • Patent number: 11088249
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 11056573
    Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
  • Publication number: 20210083056
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang