Patents by Inventor Tien-Shun Chang
Tien-Shun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240413155Abstract: A method includes forming a fin structure including a first channel layer, a sacrificial layer, and a second channel layer over a substrate; forming a dummy gate structure across the fin structure; recessing the fin structure; epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer; forming first dielectric layers to cover the first source/drain epitaxial structures, respectively; epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer; removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and forming a metal gate structure in the gate trench. The second source/drain epitaxial structures are over the first dielectric layers, respectively.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Yu LIN, Tien-Shun CHANG, Yi-Syuan SIAO, Su-Hao LIU, Chi On CHUI
-
Publication number: 20240379446Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 12100738Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.Type: GrantFiled: April 25, 2023Date of Patent: September 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
-
Publication number: 20240258114Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.Type: ApplicationFiled: April 10, 2024Publication date: August 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240258387Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.Type: ApplicationFiled: May 9, 2023Publication date: August 1, 2024Inventors: Yi-Syuan Siao, Meng-Han Chou, Chien-Yu Lin, Wei-Ting Chang, Tien-Shun Chang, Chin-I Kuan, Su-Hao Liu, Chi On Chui
-
Patent number: 11984322Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.Type: GrantFiled: May 6, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 11935793Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.Type: GrantFiled: May 29, 2020Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240055300Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ting CHANG, Kuo-Ju CHEN, Tien-Shun CHANG, Su-Hao LIU, Huicheng CHANG
-
Publication number: 20230387251Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
-
Publication number: 20230377913Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20230268423Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition having a second etch rate, the second etch rate being different from the first etch rate; etching a first recess in the first region of the substrate having the second composition and a second recess in the second region having the first composition; and epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.Type: ApplicationFiled: February 21, 2022Publication date: August 24, 2023Inventors: Tien-Shun Chang, Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20230261055Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
-
Patent number: 11670683Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.Type: GrantFiled: August 4, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
-
Patent number: 11640986Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.Type: GrantFiled: June 30, 2021Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
-
Publication number: 20230016619Abstract: A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.Type: ApplicationFiled: March 2, 2022Publication date: January 19, 2023Inventors: Tien-Shun Chang, Yu-Kang Liu, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20220359301Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 11450757Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.Type: GrantFiled: September 6, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
-
Publication number: 20220262644Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 11367621Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.Type: GrantFiled: June 15, 2020Date of Patent: June 21, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20220028707Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo