Patents by Inventor Tien Ying Luo
Tien Ying Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698269Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.Type: GrantFiled: March 3, 2016Date of Patent: July 4, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Hua Tong, Tien-Ying Luo, Yan Ping Shen, Feng Zhou, Jun Lian, Haoran Shi, Min-hwa Chi, Jin Ping Liu, Haiting Wang, Seung Kim
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Publication number: 20160190324Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.Type: ApplicationFiled: March 3, 2016Publication date: June 30, 2016Applicant: GLOBALFOUNDRIES Inc.Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
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Patent number: 9312145Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.Type: GrantFiled: March 7, 2014Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Wei Hua Tong, Tien-Ying Luo, Yan Ping Shen, Feng Zhou, Jun Lian, Haoran Shi, Min-hwa Chi, Jin Ping Liu, Haiting Wang, Seung Kim
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Patent number: 9209258Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.Type: GrantFiled: March 3, 2014Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
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Patent number: 9202697Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.Type: GrantFiled: July 19, 2013Date of Patent: December 1, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Tien-Ying Luo, Feng Zhou, Yan Ping Shen, Haiting Wang, Haoran Shi, Wei Hua Tong, Seung Kim, Yong Meng Lee
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Publication number: 20150333067Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
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Patent number: 9147696Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: GrantFiled: October 1, 2013Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
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Publication number: 20150255277Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
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Publication number: 20150249136Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.Type: ApplicationFiled: March 3, 2014Publication date: September 3, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Feng ZHOU, Tien-Ying LUO, Haiting WANG, Padmaja NAGAIAH, Jean-Baptiste LALOE, Isabelle Pauline FERAIN, Yong Meng LEE
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Publication number: 20150091094Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
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Publication number: 20150024585Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Tien-Ying LUO, Feng ZHOU, Yan Ping SHEN, Haiting WANG, Haoran SHI, Wei Hua TONG, Seung KIM, Yong Meng LEE
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Patent number: 8659087Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.Type: GrantFiled: December 16, 2009Date of Patent: February 25, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Olubunmi O. Adetutu, Tien Ying Luo, Narayanan C. Ramani
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Patent number: 8017469Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: GrantFiled: January 21, 2009Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tien-Ying Luo, Gauri V. Karve, Daniel G. Tekleab
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Publication number: 20110210401Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
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Patent number: 7981808Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.Type: GrantFiled: September 30, 2008Date of Patent: July 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tien Ying Luo, Olubunmi O. Adetutu
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Patent number: 7829447Abstract: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.Type: GrantFiled: May 19, 2006Date of Patent: November 9, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Rode R. Mora, Tab A. Stephens, Tien Ying Luo
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Patent number: 7776731Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.Type: GrantFiled: September 14, 2007Date of Patent: August 17, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kurt H. Junker, Tien-Ying Luo, Dina H. Triyoso
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Patent number: 7767588Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.Type: GrantFiled: February 28, 2006Date of Patent: August 3, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Tien Ying Luo, Rajesh A. Rao
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Publication number: 20100184260Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: ApplicationFiled: January 21, 2009Publication date: July 22, 2010Inventors: Tien-Ying Luo, Gauri V. Karve, Daniel G. Tekleab
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Patent number: RE45955Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: GrantFiled: August 6, 2014Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Tien Ying Luo, Gauri V. Karve, Daniel K. Tekleab