Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Abstract: An intelligent audio playback and community sharing system is disclosed, comprising a backend server equipment, an object body combined with an RFID tag, a sound box device, and an application program installed within an electronic device, wherein the backend server equipment stores at least one object file such that, after the object body is placed on the sound box device, the sound box device can search inside the local device or the backend server equipment and play back the audio signals corresponding to the RFID tag; moreover, the user can add or change the audio signals which each RFID tag corresponds to via the application program so that the sound box device can play back music or audio files of any suitable forms in accordance with the user's needs.

Abstract: An intelligent audio playback and community sharing system is disclosed, comprising a backend server equipment, an object body combined with an RFID tag, a sound box device, and an application program installed within an electronic device, wherein the backend server equipment stores at least one object file such that, after the object body is placed on the sound box device, the sound box device can search inside the local device or the backend server equipment and play back the audio signals corresponding to the RFID tag; moreover, the user can add or change the audio signals which each RFID tag corresponds to via the application program so that the sound box device can play back music or audio files of any suitable forms in accordance with the user's needs.

Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.

Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Abstract: A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.

Abstract: A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.

Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.

Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.

Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.

Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.

Abstract: An operating circuit includes an amplifier having a first input terminal coupled to a reference voltage; a first transconducting element for selectively generating a first current; a second transconducting element for selectively generating a second current; a resistive element having a first terminal coupled to the first transconducting element; a capacitive element having a first terminal selectively coupled to the second transconducting element; and a switching device. The switching device has a first configuration to connect the first terminal of the capacitive element to the second transconducting element and connect the first terminal of the resistive element to a second input terminal of the amplifier, and has a second configuration to disconnect the first terminal of the capacitive element from the second transconducting element and connect the second input terminal of the amplifier to the first terminal of the capacitive element instead of the first terminal of the resistive element.