Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A method for calculating a MAC operation is performed by a memory, in particular in the neuromorphic calculation field. It allows performing the scalar product between an activation vector whose elements are binary with a vector of synaptic coefficients, quantised over M>2 levels. The calculation comprises a first phase, in which M?1 reading voltages Vread2, . . . , VreadM-1 are applied to the word lines corresponding to a positive activation and the number of passing cells in a bit line is determined for each of these voltages. In a second phase, these M?1 reading voltages are applied to the word lines corresponding to a negative activation and, for each of them, the number of passing cells in the bit line is determined again. The scalar product is then deduced from the difference between the total number of passing cells in the first phase and the total number of passing cells in the second phase.

Abstract: A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M?1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

Abstract: The present invention concerns a method for programming a Bayesian neural network (BNN) in a RRAM memory. After the BNN has been trained on a dataset D, the joint posterior probability distribution of the synaptic coefficients, p(w|D) is decomposed into a mixture of multivariate mean-field Gaussian components by GMM. The weighting coefficients and the parameters of these multivariate Gaussian components are estimated by MDEM (Multi-Dimensional Expectation Maximization) with two constraints. According to the first constraint, the off-diagonal terms of the covariance matrix of each component are forced to zero. According to the second constraint, the couples of mean values and diagonal terms of the covariance matrix of each component are constrained to belong to a hardware compliance domain determined by a relationship between the conductance mean value and conductance standard deviation of a memristor programmed by a SET or RESET operation.

Abstract: This method for training a binarized neural network, also called BNN, including neurons, with a binary weight for each connection between two neurons, is implemented by an electronic circuit and comprises: a forward pass including calculating an output vector by applying the BNN on an input vector; a backward pass including computing an error vector from the calculated output vector, and calculating a new value of the input vector by applying the BNN on the error vector; a weight update including computing a product by multiplying an element of the error vector with one of the new value of the input vector, modifying a latent variable depending on the product; and updating the weight with the latent variable; each weight being encoded using a primary memory component; each latent variable being encoded using a secondary memory component having a characteristic subject to a time drift.