Patents by Inventor Tiffany Byrne
Tiffany Byrne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8193072Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: November 2, 2010Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Publication number: 20110059596Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: ApplicationFiled: November 2, 2010Publication date: March 10, 2011Inventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7897486Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: May 9, 2007Date of Patent: March 1, 2011Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7494041Abstract: A composition includes a solder paste matrix and a solder mixture including a tin-based solder alloy. The composition also includes a discrete dispersion of a metal. The tin-based alloy includes a melting first temperature and the metal includes a melting second temperature. The melting second temperature is greater than the melting first temperature. The discrete dispersion is in a particle range of a majority passing minus 520-mesh. A process includes blending the solder mixture and the metal under non-alloying conditions to achieve the discrete dispersion of the metal. A process includes reflowing the composition such that the composition when solidified, has a melting point that is higher than the solder mixture in the composition.Type: GrantFiled: June 23, 2004Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Edward L. Martin, Tiffany A. Byrne, Carl Deppisch
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Patent number: 7291548Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.Type: GrantFiled: April 17, 2007Date of Patent: November 6, 2007Assignee: Intel CorporationInventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
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Patent number: 7279362Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: March 31, 2005Date of Patent: October 9, 2007Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Publication number: 20070218652Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: ApplicationFiled: May 9, 2007Publication date: September 20, 2007Inventors: Eric Li, Daoqiang Lu, Christopher Rumer, Paul Koning, Darcy Fleming, Gudbjorg Oskarsdottir, Tiffany Byrne
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Publication number: 20070190772Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.Type: ApplicationFiled: April 17, 2007Publication date: August 16, 2007Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Eward Martin, Mohd Erwan Basiron, Wei Loh, Sheau Lim, Yoong Tatt Chin
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Patent number: 7253088Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.Type: GrantFiled: September 29, 2004Date of Patent: August 7, 2007Assignee: Intel CorporationInventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
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Publication number: 20060223284Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Inventors: Eric Li, Daoqiang Lu, Christopher Rumer, Paul Koning, Darcy Fleming, Gudbjorg Oskarsdottir, Tiffany Byrne
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Publication number: 20060067852Abstract: A composition includes a tin-containing solder with a melting temperature below about 150° C. The tin-containing solder includes indium, tin, and bismuth as alloy elements, and optionally contains a doping material and/or a second-phase dispersiod. A process includes blending the tin-containing solder under non-alloying conditions to achieve the discrete dispersion of the doping material. A process also includes blending the tin-containing solder with the particulate to achieve the discrete dispersion of the particulate. The composition is also combined with a microelectronic device to form a package. The composition is also combined with a microelectronic device and at least one I/O functionality to form a computing system.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Inventors: Daewoong Suh, Tiffany Byrne, Melissa Baeten, Edward Martin
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Publication number: 20060068579Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Edward Martin, Mohd Erwan Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt Chin
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Publication number: 20060060639Abstract: According to one aspect of the invention, a contact formation and an electronic assembly incorporating the contact formation are provided. The contact formation may include a low temperature solder material and a plurality of dopant material particles within the solder material. The dopant material may include at least one of an insoluble metal, an intermetallic compound, and an oxide. The low temperature solder material may have a first liquidus temperature, and the contact formation may have a second liquidus temperature. The second liquidus temperature may be approximately the same as the first liquidus temperature.Type: ApplicationFiled: September 21, 2004Publication date: March 23, 2006Inventors: Tiffany Byrne, Edward Martin, Carl Deppisch, Daewoong Suh
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Publication number: 20050284918Abstract: A composition includes a solder paste matrix and a solder mixture including a tin-based solder alloy. The composition also includes a discrete dispersion of a metal. The tin-based alloy includes a melting first temperature and the metal includes a melting second temperature. The melting second temperature is greater than the melting first temperature. The discrete dispersion is in a particle range of a majority passing minus 520-mesh. A process includes blending the solder mixture and the metal under non-alloying conditions to achieve the discrete dispersion of the metal. A process includes reflowing the composition such that the composition when solidified, has a melting point that is higher than the solder mixture in the composition.Type: ApplicationFiled: June 23, 2004Publication date: December 29, 2005Inventors: Edward Martin, Tiffany Byrne, Carl Deppisch