Abstract: In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Abstract: In one embodiment, a detection unit includes a sequence providing unit to provide a third group of derived sequences. The sequence providing unit has a counting unit and multiplexers connected to the counting unit. Fixed values are applied at the inputs of the multiplexers and the sequence providing unit provides the derived sequences of the third group at the outputs of the multiplexers. The third group for each first pseudo noise (PN) sequence has a derived sequence assigned to the first PN sequence. The detection unit includes a correlation unit, which is connected to the sequence providing unit and formed to calculate correlation results by correlating the differentially demodulated signal with each derived sequence of the third group. The detection unit includes an evaluation unit, which is connected to the correlation unit and is formed to derive the values of the data symbols by evaluating the correlation results.

Abstract: A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

Abstract: A method for the transmission and use of a power amplifier and transmission circuit of a radio network is provided that includes a power amplifier, which is connectable to an antenna, a counter whose output is connected to a control input of the power amplifier to output a count value to control the amplification of the power amplifier, a register for storing a register value, a comparator whose inputs are connected to the output of the counter and the register for comparing the register value with the count value, and a control circuit whose input is connected to the comparator and whose output is connected to the counter to control a counting process depending on the comparison result of the comparator.

Abstract: In one embodiment, a cell of an integrated circuit includes a master-slave flip-flop and comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the master-slave flip-flop, and an inverted output signal of the master-slave flip-flop. The master-slave flip-flop comprises a master flip-flop and a slave flip-flop. The slave flip-flop includes a first inverting element and a second inverting element. An output of the first inverting element is connectable to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element. To output the output signal and the inverted output signal of the master-slave flip-flop, the output and the input of the second inverting element are connectable to the inputs of the comparator logic.

Abstract: A receiver and method for operating a receiver, in particular of a radio network, is provided, whereby the receiver includes circuit blocks in a receive path for detecting a preamble of a received signal, and a controller for controlling a receive mode. Whereby at least some of the circuit blocks are designed to be capable of being turned on for a turn-on duration and turned off for a turn-off duration. Whereby, the controller is configured to alternately turn on at least some of the circuit blocks for the turn-on duration and off for the turn-off duration during the receive mode, wherein the turn-off duration is shorter than the preamble.

Abstract: A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

Abstract: A circuit of a node in a radio network and method for transit time measurement between a first node and a second node of a radio network is provided. A frame is transmitted by the first node, wherein the frame requires an acknowledgment of reception by the second node. A first point in time of the transmission of the frame is established by the first node by a time counter. The frame is received by the second node at a second point in time. The acknowledgment is transmitted by the second node to the first node at a third point in time, wherein the third point in time depends on the second point in time by a predetermined time interval between the second point in time and the third point in time. A fourth point in time is established by the first node by the time counter when the acknowledgment is received.

Abstract: A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

Abstract: An integrated circuit and a standard cell of an integrated circuit, having a master-slave flip-flop, having a comparator logic at whose inputs the input signal of the master-slave flip-flop, the inverted input signal of the master-slave flip-flop, the output signal of the master-slave flip-flop, and the inverted output signal of the master-slave flip-flops are present, wherein the master-slave flip-flop has a master flip-flop and a slave flip-flop, wherein the slave flip-flop has a first inverting element and a second inverting element. Whereby for feedback, an output of the first inverting element is connected to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element.

Abstract: A circuit and a method for operating a node in a radio network, whereby nodes of the same radio network have a common network ID and each node individually is assigned a node ID, wherein during the reception of a current packet by a receiving circuit of the node, an address contained in the packet is determined, wherein reception of the current packet is continued when the determined address agrees with the network ID of the node and the node ID of the node, and wherein during reception of the current packet, the reception of the current packet is terminated and the receiving circuit is controlled based on a case decision, when the determined address does not agree with the network ID of the node or the node ID of the node.

Abstract: A circuit and a method for operating the circuit of a node of a radio network, wherein a frame, which requires an acknowledgement of the reception, is received by the circuit. A receive power and/or a signal quality of the frame is determined by the circuit. A transmit power for the acknowledgement is adjusted by the circuit based on the determined receive power of the associated frame and/or the determined signal quality of the associated frame, and the acknowledgement is sent with the adjusted transmit power.

Abstract: The invention relates to a detection unit for detecting data symbols which are contained in a differentially demodulated signal and to which one respective PN sequence from a supply of sequences can be allocated at the transmission end. The inventive detection unit comprises the following units: a) a sequence supplying unit that is configured for supplying a third group of derived sequences.

Abstract: A circuit, system, and method for range finding between two nodes of a radio network, in particular in conformance with the industry standard IEEE 802.15.4. A mode for finding the range to a second node is initiated by the first node. A command for range finding with the address of the second node is transmitted from the first node to the second node in the mode for range finding. The second node is switched into the range finding mode by the command. A sequence is controlled by the command in the range finding mode. As a result of the control by the command, a first signal is transmitted by the first node in a transmission time window of the sequence and the first signal is received by the second node in an associated reception time window of the sequence, and a first phase value of the first signal is measured.

Abstract: A method for a rate increase and a method for a rate reduction of a sampling input sequence into a sampling output sequence is provided. The sampling input sequence is subjected to signal processing. Signal processing maps a spreading with a first factor and an interpolation and a decimation with a second factor to generate the sampling output sequence with use of a counter. The counter and the signal processing are clocked with the higher rate, in each case, of the sampling input sequence or the sampling output sequence, respectively.

Abstract: A transmission circuit and method for transmitting a bit sequence to be transmitted is provided that includes a dividing device for dividing the bit sequence into an even-numbered bit sequence and into an odd-numbered bit sequence, a first device for forming the first sampled values of a first fundamental wave depending on the even-numbered bit sequence, a second device for forming second sampled values of a second fundamental wave depending on the odd-numbered bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period, and includes a summator for summation of the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.

Abstract: A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

Abstract: A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

Abstract: A digital radio network, a circuit of a node of a digital radio network, and method for setting up a digital radio network is provided, wherein a transmission power of the first node is set for a radio link between a first node of the digital radio network and a second node of the digital radio network. A sensitivity of a receiving circuit of the second node is set by programming a threshold with which a field-strength-dependent signal is compared. Signal processing of a received and digitized received signal by the second node is activated when the field-strength-dependent signal reaches or exceeds the programmed threshold.

Abstract: A receiving circuit, method for receiving a signal, and use of a detection circuit and a control circuit of a receiving circuit of a node of a radio network is provided to deactivate an analog signal processing and/or determination of digital data from a signal received over an antenna of the node, when a stored current frame of the digital data has been recognized as valid, and to activate the analog signal processing and/or the determination, when the transmission of the current frame over an interface of the control circuit has been confirmed, whereby the control circuit is connected to the detection circuit and/or an input circuit for deactivation and activation, and whereby the detection circuit is formed to determine the digital data from the received signal.