Abstract: A CMOS static RAM and CMOS logic gate array are combined on a single substrate to form a new CMOS logic masterslice. The RAM includes dual port capability whereby two independent address and data paths access a common memory cell. The logic gate array includes a large number of logic blocks that may be selectively customized to provide system needed logic functions. Two metal interconnect layers are employed to provide the desired interconnections between the RAM and gate array elements. In a preferred embodiment, the masterslice contains a 128.times.9 dual port static RAM, 586 blocks of gate array logic (each block being the equivalent of two-2 input logic gates), 96 I/O pads, and 8 power pads. In this embodiment, the masterslice may be realized on a substrate having a size of approximately 5.8 mm by 6.05 mm, and exhibiting typical address access times of 20 ns and write pulse widths of less than 15 ns.