Abstract: Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Abstract: A clip-bonded semiconductor package including: a semiconductor die including a bond pad on a top side of the semiconductor die, the bond pad is arranged to receive a bond clip, the bond clip is also arranged to provide electrical connection to the bond pad via a connection part of the bond clip, the bond clip further includes a buffer layer provided to at least the connection part. A hardness of a material of the buffer layer is lower than a hardness of a material of the bond clip.

Abstract: A semiconductor device and manufacturing method thereof are presented. The device has a top side and a bottom side and includes a leadframe with pads extending to the bottom side of and exterior to the device. At least one of the pads includes a leadframe vertical protrusion extending from the bottom side to the top side. A die is flip-chip arranged in the semiconductor device and includes terminals. At least one of the terminals on the top side of the die and facing the bottom side of the device is electrically connected to a corresponding pad. Another one of the terminals on the bottom side of the die faces the top side of the device where a conductive film electrically connects the terminal to the leadframe vertical protrusion at the top side.

Abstract: A semiconductor device has one or more substrate layers, one or more epitaxy layers positioned above the one or more substrate layers, and a buffer layer directly in between the one or more substrate layers and the one or more epitaxy layers. The substrate layer can be a high-doped Arsenic layer. The epitaxy layer can be low-doped. The buffer layer can be a highly Phosphorous-doped Silicon layer. The buffer layer can be relatively thin, about 1 ?m to 5 ?m. A method includes providing a substrate layer, creating a buffer layer on top of the substrate layer; and creating an epitaxy layer on top of the buffer layer.

Abstract: A semiconductor power device has a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. An active area and a termination area adjacent the active area are arranged in the epitaxial layer. The termination area has a plurality of first rings of a first polarity and a plurality of second rings of a second polarity different from the first polarity. The semiconductor substrate and the epitaxial layer are of the second polarity. A dopant concentration in the epitaxial layer associated with the second polarity is smaller than a dopant concentration in the second rings associated with the second polarity. The termination area has a first portion directly adjacent to the active area and a second portion spaced apart from the active area by the first portion. The plurality of first rings and second rings are arranged in the second portion.

Abstract: The present disclosure presents a semiconductor device including a semiconductor body, and the semiconductor body includes one or more recessed regions in a P doped Junction Termination Extension (JTE) region, and a depth of the recessed regions is smaller than a depth of the JTE region, and an N+ implant at a top surface of the JTE region, so that the N+ implant forms a part of mesa regions in between the recessed regions. A method of manufacturing such a semiconductor device is also presented.

Abstract: The present disclosure presents a semiconductor device including a semiconductor body, and the semiconductor body includes one or more recessed regions in a P doped Junction Termination Extension (JTE) region, and a depth of the recessed regions is smaller than a depth of the JTE region, and an N+ implant at a bottom of the recessed regions. A method of manufacturing such a semiconductor device is also presented.

Abstract: A semiconductor device is provided, including a semiconductor body having a semiconductor substrate and an epitaxial layer on the substrate, the epitaxial layer being a first conductivity type, and an active area and a termination area adjacent the active area are in the epitaxial layer, the termination area includes a plurality of laterally spaced apart first regions, the first regions being a second conductivity type opposite to the first type, the plurality of first regions enclosing, observed from a top view of the semiconductor device, the active area and one or more second regions, the second regions are in between the plurality of spaced apart first regions, respectively, the one or more second regions extend further into the epitaxial layer than the plurality of first regions, and the one or more second regions include an insulation material for insulating the plurality of first regions from one another.

Abstract: The present disclosure relates to a method of improving semiconductor package creepage, the package includes a semiconductor device, and a plurality of electrically conductive contacts at a surface of the package, the package includes insulating material for electrically insulating the package between the plurality of electrically conductive contacts, an initial creepage distance is defined by the shortest distance over the surface of the package between two of the plurality of contacts, and the method includes the steps of applying a coating over at least part of the insulating material of the package, and the coating has an electrical volume resistivity higher than an electrical volume resistivity of the insulating material of the package to increase the initial creepage distance and improve package creepage of the semiconductor package.

Abstract: A vertically oriented semiconductor device including a semiconductor body, the semiconductor device having a first major surface and includes a substrate, a first region provided on the substrate and having a first conductivity type, a metal layer provided on top of the first region, so that a Schottky junction is provided between the first region and the metal layer, two laterally spaced islands, extending from the first major surface downward into the semiconductor body, the islands have the second conductivity type, the first region includes an epitaxial layer provided on the substrate, and an N-current spreading (NCS), layer provided on top of the epitaxial layer, a doping concentration of the epitaxial layer is lower than a doping concentration of the NCS layer, and the NCS layer at least covers sidewalls of the two islands.

Abstract: A vertically oriented semiconductor device including a semiconductor body, having a first major surface and a substrate, a first region, provided on the substrate and a first conductivity type, the first region having a first doping concentration, a metal layer provided on top of the first region, so that a Schottky junction is provided between the first region and the metal layer, at least two, laterally spaced islands, extending from the first major surface downward into the semiconductor body, the islands having the second conductivity type. The semiconductor device includes a surface layer, provided between the first region and the metal layer, and provided, laterally, in between the at least two, laterally spaced, islands, the surface layer is of a second conductivity type, opposite to the first conductivity type, the surface layer having a second doping concentration being in a range of 5%-20% of the first doping concentration.

Abstract: The disclosure relates to an electrical contact structure, and corresponding method of manufacturing an electrical contact structure, for a discrete semiconductor device. The electrical contact includes a first metal layer configured and arranged to contact a strained active area of a semiconductor die, a second metal layer configured and arranged to contact the first metal layer, and a third metal layer configured and arranged to contact the second metal layer.

Abstract: A method of manufacturing a semiconductor package is provided, with an integrated heatsink and electrical connection feature. The semiconductor die can be attached to the terminal using eutectic bonding, preferably CuSn eutectic, Ag containing adhesives or Ag sintering material. These bondings are lead (Pb) free connection methods, which make the finished semiconductor package RoHS compliant (restriction of hazardous materials).

Abstract: A semiconductor package assembly and molding resin case is provided. The package includes a lead frame having a first and a second lead frame side opposite to the first; a semiconductor die structure having a first and a second die side opposite to the first, the die structure being mounted with its second die side on the first lead frame side, resulting in a first connection; a bond element connected to the first die of the die structure, resulting in another connection; with the molding resin case encapsulating at least the die structure, the lead frame and a first part of at least one bond element connected to the die structure, leaving the second lead frame side and the at least one bond element partly exposed; and at least one bond element is provided with electric field modulation structures configured to alter an electric field created between the connections.

Abstract: The present disclosure relates to a method of improving semiconductor package creepage. The package includes a semiconductor device, and a plurality of electrically conductive contacts at a surface of the package, the package includes insulating material for electrically insulating the package between the plurality of electrically conductive contacts and an initial creepage distance is defined by the shortest distance over the surface of the package between two of the plurality of contacts, and the method includes the steps of: applying a layer of insulating material over at least part of at least one of the two contacts, the insulating material is applied in a thin layer and selected to obtain a package thermal resistance increase less than a factor 3 as compared to an uncoated semiconductor package, to increase the initial creepage distance and improve package creepage of the semiconductor package.

Abstract: Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Abstract: A vertical semiconductor device and method for manufacturing the same is provided. The semiconductor device includes a body with a substrate and an epitaxial layer on the substrate, the layer includes a first region of a first conductivity type, and a second region of a second different conductivity type, the second region is arranged opposite to the substrate with respect to the first region, and when viewed in a first direction from the layer to the substrate, the first region and the second region each extend across an entire area of the body. The device further includes a trench arranged in the body, extending through the second region and at least partially into the first region, thereby dividing the second region into an inner and an outer portion that are mutually electrically isolated, and a first conductive contact on the second region to enable electrically accessing the inner portion.

Abstract: A semiconductor device having an improved junction termination extension region is provided. The disclosure particularly relates to diodes having such an improved junction termination extension. The semiconductor device includes an active area extending in a first direction, and a junction termination extension, ‘JTE’, region of a first charge type surrounding the active area. The JTE region includes a plurality of field relief sub-regions that each surround the active area and that are mutually spaced apart in a direction perpendicular to a circumference of the active area. The plurality of field relief sub-regions includes a first group of field relief sub-regions, and for each field relief sub-region of the first group, a plurality of field relief elements of a second charge type is provided therein, which field relief elements are mutually spaced apart in a circumferential direction with respect to the active area.

Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.

Abstract: A vertical oriented semiconductor device is provided that includes a semiconductor body having a first major surface, the semiconductor body includes a first region of a first conductivity type, a second region of a second conductivity type, and the second region is adjacent the first region so that a junction is provided between the first region and the second region. The junction has a maximum distance to the first major surface, and the semiconductor device further includes a trench extending into the semiconductor body from the first major surface to an extension depth at least equal to the maximum distance. The trench includes a material arranged to provide electrical insulation to limit a lateral field termination distance associated with the junction.