Patents by Inventor Tim Baldauf

Tim Baldauf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347760
    Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 9, 2019
    Assignees: Technische Universität Dresden, NaMLab gGmbH
    Inventors: Tim Baldauf, André Heinzig, Walter Michael Weber
  • Publication number: 20180012996
    Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.
    Type: Application
    Filed: June 20, 2017
    Publication date: January 11, 2018
    Applicants: Technische Universität Dresden, NaMLab gGmbH
    Inventors: Tim BALDAUF, André HEINZIG, Walter Michael WEBER
  • Patent number: 9484407
    Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Stefan Flachowsky
  • Publication number: 20150129964
    Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.
    Type: Application
    Filed: August 27, 2014
    Publication date: May 14, 2015
    Inventors: Tim Baldauf, Stefan Flachowsky
  • Patent number: 8941187
    Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Patent number: 8916928
    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Patent number: 8912606
    Abstract: Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Patent number: 8835255
    Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Stefan Flachowsky, Tom Hermann, Ralf Illgen
  • Publication number: 20140206157
    Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Stefan Flachowsky, Tom Herrmann, Ralf Illgen
  • Publication number: 20140027825
    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Patent number: 8580643
    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130277746
    Abstract: Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tim Baldauf, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130181299
    Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130049121
    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen