Abstract: An apparatus includes at least one housing configured to be implanted on or within a recipients body. The apparatus further includes first circuitry configured to wirelessly receive power from a device external to the recipients body, second circuitry configured to provide stimulation signals to a portion of the recipients body, and at least one power storage device having a discharged state in which the at least one power storage device is discharged to a voltage below a minimum operating voltage of the at least one power storage device. The apparatus further includes third circuitry configured to, while the at least one power storage device is in the discharged state, controllably distribute the power simultaneously to both the second circuitry and the at least one power storage device.

Abstract: An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer ?2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An image sensor (10) comprises an array of pixels (11) having a subset of pixels (12). The subset of pixels (12) comprises a first and a second pixel (20, 30), wherein the first and the second pixel (20, 30) each comprises a pinned photodiode (21, 31), a sense node (22, 32), a transfer gate (23, 33) coupled to the pinned photodiode (21, 31) and the sense node (22, 32), and a connection switch (24, 34) coupled to the sense node (22, 32). The subset of pixels (12) further comprises a common reset node (40) such that the connection switch (24, 34) of the first and the second pixel (20, 30) are coupled to the common reset node (40), and a single reset transistor (41) providing a reset voltage (VRES) to the common reset node (40). The first and the second pixel (20, 30) share the single reset transistor (41).

Abstract: An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer?2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.