Patents by Inventor Tim Botsford

Tim Botsford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR ALIGNMENT OF AN INTEGRATED CIRCUIT
    Publication number: 20210407840
    Abstract: The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Jean-Philippe Fricker, Tim Botsford, Philip Ferolito, Paul Kennedy
  • System and method for alignment of an integrated circuit
    Patent number: 11145530
    Abstract: The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: October 12, 2021
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Tim Botsford, Philip Ferolito, Paul Kennedy
  • SYSTEM AND METHOD FOR ALIGNMENT OF AN INTEGRATED CIRCUIT
    Publication number: 20210143041
    Abstract: The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 13, 2021
    Inventors: Jean-Philippe Fricker, Tim Botsford, Philip Ferolito, Paul Kennedy