Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Abstract: A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Abstract: A Doherty amplifier circuit includes an RF input terminal, an RF output terminal, a main amplifier having a first input terminal and a first output driving terminal, and a peaking amplifier having a second input terminal and a second output driving terminal. An output combining network is configured to feed output current from the first and second output driving terminals into a summing node. The output combining network includes a transmission line transformer balun having first and second input ports and a first output port being connected to the summing node, a first electrical connection between the first output driving terminal and the first input port, and a second electrical connection between the second output driving terminal and the second input port. The second electrical connection includes a quarter wave impedance inverter. A first output impedance matching network is connected between the summing node and the RF output terminal.