Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure.