Patents by Inventor Tim Coe

Tim Coe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9130594
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Microsemi Communications, Inc.
    Inventor: Tim Coe
  • Publication number: 20150046777
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Applicant: Vitesse Semiconductor Corporation
    Inventor: Tim Coe
  • Patent number: 8887021
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 11, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Tim Coe
  • Patent number: 8705603
    Abstract: Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: April 22, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Tim Coe, Greg Warwar
  • Publication number: 20130013972
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: Vitesse Semiconductor Corporation
    Inventor: Tim Coe
  • Patent number: 8276047
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 25, 2012
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Tim Coe
  • Publication number: 20100122149
    Abstract: Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 13, 2010
    Inventor: Tim Coe
  • Publication number: 20090274206
    Abstract: Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.
    Type: Application
    Filed: February 5, 2009
    Publication date: November 5, 2009
    Inventors: Tim Coe, Greg Warwar
  • Patent number: 6948109
    Abstract: A forward correction system using a linked low density parity check (LDPC) code. The linked LDPC code is formed by extending a portion of an original LDPC matrix such that the LDPC code becomes a periodic repeating code.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: September 20, 2005
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Tim Coe
  • Patent number: 6738922
    Abstract: A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The frequency detection circuit includes a digital phase tracking circuit (DPTC), which uses a rotational phase shifter to shift phase of a variable clock signal from a voltage controlled oscillator in the PLL circuit, in discrete amounts from 0 to 360 degrees, depending on a digital input code provided by a digital accumulator, which receives up or down count signals from a phase comparator. The shifted variable clock signal is provided to a phase/frequency detector, which provides an output to a glitch suppressor to suppress small phase differences prior to providing the output to the PLL circuit. When the frequency difference between the variable clock signal and the reference clock signal is large, the phase/frequency detector drives the frequency in the correct direction.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: May 18, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Greg Warwar, Tim Coe
  • Publication number: 20030079171
    Abstract: A forward correction system using a linked low density parity check (LDPC) code. The linked LDPC code is formed by extending a portion of an original LDPC matrix such that the LDPC code becomes a periodic repeating code.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 24, 2003
    Inventor: Tim Coe