Abstract: A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another.

Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.

Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.

Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.

Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.

Abstract: A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another.

Abstract: An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain “buffered” output signals therefrom with symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two stages of differential amplifier pairs (i.e., a total of 4 separated differential amplifiers). The differential amplifiers in the first stage convert the single-ended input signal to a full-differential signal, which is then converted back to a single-ended output signal by the differential amplifier pair in the second stage. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross” coupled structure.

Abstract: A memory device with a low power control circuit that reduces power while ensuring that the device remains in a low power mode until a high power mode has been requested. The low power control circuit initially monitors a control signal using a CMOS buffer or inverter while a reference voltage is grounded or floated. Upon CMOS detection of a signal indicating that a high power mode is required, the low power control circuit monitors the signal using a differential amplifier and the specified reference voltage (i.e., ungrounded and un-floated reference voltage) to determine if the low power mode should be exited. In doing so, the low power control circuit prevents noise from inadvertently causing the device to exit the low power mode while at the same time reduces the power in the device.

Abstract: A memory device with a low power control circuit that reduces power while ensuring that the device remains in a low power mode until a high power mode has been requested. The low power control circuit initially monitors a control signal using a CMOS buffer or inverter while a reference voltage is grounded or floated. Upon CMOS detection of a signal indicating that a high power mode is required, the low power control circuit monitors the signal using a differential amplifier and the specified reference voltage (i.e., ungrounded and un-floated reference voltage) to determine if the low power mode should be exited. In doing so, the low power control circuit prevents noise from inadvertently causing the device to exit the low power mode while at the same time reduces the power in the device.