Abstract: A method of controlling access to memory by a processing element in a plurality of processing elements arranged in a single instruction multiple data (SIMD) processing array is disclosed. Each processing element includes an internal memory unit, and a register file. The method comprises retrieving an address value from the register file of the processing element, the address value relating to an address in the internal memory of the processing element, and accessing the internal memory on the basis of the address value.

Abstract: A data transfer controller for controlling transfer of data items in a data processing system comprising a single instruction multiple data (SIMD) array of processing elements is disclosed. The controller comprises a transfer controller operable to control transfer of data to and/or from an internal memory unit of a processing element in said array, each processing element including a processing unit and an internal memory unit, the transfer controller being operable such that data transfer to and/or from the internal memory unit is performed independently of the operation of the processing unit of the processing element concerned. Operation by said processing unit on a predetermined type of instruction may be blocked until after said data transfer is complete or, if said data transfer started after said operation commenced, said data transfer may be blocked until after said operation is complete.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.

Abstract: A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

Abstract: A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements in which the processing elements are arranged in a plurality of SIMD processing blocks, comprises determining which instruction stream has priority at a particular moment in time, and transferring that determined instruction stream to the SIMD array.

Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Abstract: A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes at least one redundant processing element for processing data intended for a faulty processing element of the array.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing graphical data. A memory unit external to the array is utilised for storage of processed graphical data.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to determine which of a plurality of instruction streams has priority at a particular moment in time, and to transfer that instruction stream to the SIMD array.

Abstract: A method for supplying instructions to a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, the method comprising retrieving instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, combining the plurality of instruction streams into a plurality of output instruction streams for supply to respective ones of the processor arrays, and distributing the output instruction streams to respective ones of the processor arrays.

Abstract: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

Abstract: A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements.

Abstract: A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays.

Abstract: A data processor comprises a plurality of processing elements arranged in a first plurality of SIMD (single instruction multiple data) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to transfer at least one instruction stream, and to transfer received instruction streams to at least one of the first plurality of processing arrays.

Abstract: An apparatus and method for rendering multiplanar reformatting (MPR) images of volume data to be displayed to a user. The apparatus may comprise a conventional personal computer system having a central processing unit (CPU) coupled to a system memory for storing the volume data and a graphics processing unit (GPU) having a GPU memory connected to the computer bus. The computer system CPU is configured to predict an MPR image which may be required for display at a future time and to identify blocks of voxels comprising the volume data which will be needed to render the predicted MPR image. The CPU is further operable to retrieve these blocks from the system memory and to queue them for transfer to the GPU memory. The transfer of blocks from the queue to the GPU memory is controlled by a scheduler such that at least some of the queued blocks are transferred to the GPU memory prior to the predicted MPR image becoming required for display.