Patents by Inventor Tim Foley

Tim Foley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10152820
    Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Tim Foley
  • Patent number: 9870640
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 16, 2018
    Assignee: INTEL CORPORATION
    Inventors: Rahul P. Sathe, Tim Foley
  • Publication number: 20160321834
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 3, 2016
    Applicant: Intel Corporation
    Inventors: RAHUL P. SATHE, TIM FOLEY
  • Patent number: 9449419
    Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Rahul P. Sathe, Tim Foley, Karthik Vaidyanathan
  • Patent number: 9449420
    Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Rahul P. Sathe, Tim Foley
  • Patent number: 9208602
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 8, 2015
    Assignee: INTEL CORPORATION
    Inventors: Rahul P. Sathe, Tim Foley
  • Publication number: 20150091913
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: RAHUL P. SATHE, TIM FOLEY
  • Publication number: 20140267345
    Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 18, 2014
    Inventors: Robert M. Toth, Tim Foley
  • Publication number: 20140198120
    Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 17, 2014
    Inventors: Rahul P. Sathe, Tim Foley
  • Publication number: 20130257891
    Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
    Type: Application
    Filed: September 27, 2012
    Publication date: October 3, 2013
    Inventors: Rahul P. Sathe, Tim Foley, Karthik Vaidyanathan
  • Patent number: 7928278
    Abstract: The subject invention pertains to a method, apparatus, and composition of matter for producing near-infrared (near-IR) radiation. The subject invention can incorporate a polymer and a metal-containing compound, wherein the metal-containing compound can incorporate a metal-ligand complex, wherein when the metal-ligand complex becomes excited, energy is transferred from the ligand to the metal, wherein, the energy transferred to the metal by sensitization is emitted as near-infrared radiation. In a specific embodiment, the subject invention relates to a composition of matter having a luminescent polymer and a metal containing compound where the metal containing compound incorporates a metal-ligand complex such that the absorption spectrum of the metal-ligand complex at least partially overlaps with the emission spectrum of the luminescent polymer.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: April 19, 2011
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Kirk S. Schanze, John R. Reynolds, James M. Boncella, Paul H. Holloway, Benjamin Scott Harrison, Tim Foley, Sriram Ramakrishnan
  • Publication number: 20020197050
    Abstract: The subject invention pertains to a method, apparatus, and composition of matter for producing near-infrared (near-IR) radiation. The subject invention can incorporate a polymer and a metal-containing compound, wherein the metal-containing compound can incorporate a metal-ligand complex, wherein when the metal-ligand complex becomes excited, energy is transferred from the ligand to the metal, wherein, the energy transferred to the metal by sensitization is emitted as near-infrared radiation. In a specific embodiment, the subject invention relates to a composition of matter having a luminescent polymer and a metal containing compound where the metal containing compound incorporates a metal-ligand complex such that the absorption spectrum of the metal-ligand complex at least partially overlaps with the emission spectrum of the luminescent polymer.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 26, 2002
    Inventors: Kirk S. Schanze, John R. Reynolds, James M. Boncella, Paul H. Holloway, Benjamin Scott Harrison, Tim Foley, S. Ramakrishnan