Patents by Inventor Tim Foley
Tim Foley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10152820Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.Type: GrantFiled: December 17, 2013Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Robert M. Toth, Tim Foley
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Patent number: 9870640Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.Type: GrantFiled: December 7, 2015Date of Patent: January 16, 2018Assignee: INTEL CORPORATIONInventors: Rahul P. Sathe, Tim Foley
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Publication number: 20160321834Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.Type: ApplicationFiled: December 7, 2015Publication date: November 3, 2016Applicant: Intel CorporationInventors: RAHUL P. SATHE, TIM FOLEY
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Patent number: 9449419Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.Type: GrantFiled: September 27, 2012Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Rahul P. Sathe, Tim Foley, Karthik Vaidyanathan
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Patent number: 9449420Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.Type: GrantFiled: December 30, 2011Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Rahul P. Sathe, Tim Foley
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Patent number: 9208602Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.Type: GrantFiled: September 27, 2013Date of Patent: December 8, 2015Assignee: INTEL CORPORATIONInventors: Rahul P. Sathe, Tim Foley
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Publication number: 20150091913Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: RAHUL P. SATHE, TIM FOLEY
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Publication number: 20140267345Abstract: Various embodiments provide for a new texture address mode that excludes any texture filter taps (i.e. coordinates) that fall outside the texture domain from the filtering process. Taps outside a texture domain are not considered in one embodiment. Also, various embodiments provide flexibility as to the texture coordinate locations ti and values of weights wi. The tap weight can be modified as a function of tap location and in particular whether a tap is within a texture.Type: ApplicationFiled: December 17, 2013Publication date: September 18, 2014Inventors: Robert M. Toth, Tim Foley
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Publication number: 20140198120Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.Type: ApplicationFiled: December 30, 2011Publication date: July 17, 2014Inventors: Rahul P. Sathe, Tim Foley
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Publication number: 20130257891Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.Type: ApplicationFiled: September 27, 2012Publication date: October 3, 2013Inventors: Rahul P. Sathe, Tim Foley, Karthik Vaidyanathan
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Patent number: 7928278Abstract: The subject invention pertains to a method, apparatus, and composition of matter for producing near-infrared (near-IR) radiation. The subject invention can incorporate a polymer and a metal-containing compound, wherein the metal-containing compound can incorporate a metal-ligand complex, wherein when the metal-ligand complex becomes excited, energy is transferred from the ligand to the metal, wherein, the energy transferred to the metal by sensitization is emitted as near-infrared radiation. In a specific embodiment, the subject invention relates to a composition of matter having a luminescent polymer and a metal containing compound where the metal containing compound incorporates a metal-ligand complex such that the absorption spectrum of the metal-ligand complex at least partially overlaps with the emission spectrum of the luminescent polymer.Type: GrantFiled: June 12, 2002Date of Patent: April 19, 2011Assignee: University of Florida Research Foundation, Inc.Inventors: Kirk S. Schanze, John R. Reynolds, James M. Boncella, Paul H. Holloway, Benjamin Scott Harrison, Tim Foley, Sriram Ramakrishnan
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Publication number: 20020197050Abstract: The subject invention pertains to a method, apparatus, and composition of matter for producing near-infrared (near-IR) radiation. The subject invention can incorporate a polymer and a metal-containing compound, wherein the metal-containing compound can incorporate a metal-ligand complex, wherein when the metal-ligand complex becomes excited, energy is transferred from the ligand to the metal, wherein, the energy transferred to the metal by sensitization is emitted as near-infrared radiation. In a specific embodiment, the subject invention relates to a composition of matter having a luminescent polymer and a metal containing compound where the metal containing compound incorporates a metal-ligand complex such that the absorption spectrum of the metal-ligand complex at least partially overlaps with the emission spectrum of the luminescent polymer.Type: ApplicationFiled: June 12, 2002Publication date: December 26, 2002Inventors: Kirk S. Schanze, John R. Reynolds, James M. Boncella, Paul H. Holloway, Benjamin Scott Harrison, Tim Foley, S. Ramakrishnan