Abstract: A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward unit processes a signal for transmission, a feedback unit coupled to the feed forward unit, the feedback unit generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit, a closed loop power control unit coupled to the feedback unit and to the feed forward unit, the closed loop power control unit generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source or software instructions, and a ramp path power control unit coupled to the data source, the ramp path power control unit generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A power control loop includes a feed forward unit 301 coupled to a data source, the feed forward unit 301 processes a signal for transmission, a feedback unit 302 coupled to the feed forward unit 301, the feedback unit 302 generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit 301, a closed loop power control unit 303 coupled to the feedback unit 302 and to the feed forward unit 301, the closed loop power control unit 303 generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source, and a ramp path power control unit 304 coupled to the data source, the ramp path power control unit 304 generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward unit processes a signal for transmission, a feedback unit coupled to the feed forward unit, the feedback unit generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit, a closed loop power control unit coupled to the feedback unit and to the feed forward unit, the closed loop power control unit generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source or software instructions, and a ramp path power control unit coupled to the data source, the ramp path power control unit generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward unit processes a signal for transmission, a feedback unit coupled to the feed forward unit, the feedback unit generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit, a closed loop power control unit coupled to the feedback unit and to the feed forward unit, the closed loop power control unit generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source, and a ramp path power control unit coupled to the data source, the ramp path power control unit generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A novel apparatus for and method of delay alignment in a closed loop two-point modulation all digital phase locked loop (ADPLL). The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison.

Abstract: A digital phase lock loop (DPLL) system and method employ digital loop control and a digital controller to drive the DPLL oscillator with fast re-lock capability. The DPLL optionally uses low power retention flops to implement low power and fast interrupt services.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: A non-linear time digitizer delay chain and a respective lookup table for converting the phase error into a digital code together prevent a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the phase error pulse associated with a digital phase lock loop (PLL) can be measured and represented in more meaningful and accurate ways that that achievable when using a conventional T2d circuit to convert the phase error into a digital code. The lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D.

Abstract: A non-linear time digitizer delay chain and a respective lookup table for converting the phase error into a digital code together prevent a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the phase error pulse associated with a digital phase lock loop (PLL) can be measured and represented in more meaningful and accurate ways that that achievable when using a conventional T2d circuit to convert the phase error into a digital code. The lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.