Abstract: The present invention provides circuitry for compensating the slew rate of an output buffer so as to reduce the magnitude of the variation in slew rate and ground bounce due to temperature and processing variations. The circuitry includes structure at the gate of each transistor that supplies or sinks current to charge or discharge capacitance at the output buffer output that slows down the turn on of the output transistors as temperature or process shifts in a way that would tend to increase the current carrying capability of the output transistor. The structure includes a transmission gate having its source connected to the gate of the output transistor, its drain connected to a capacitor, and its gate connected such that it is conducting.

Abstract: The present invention provides power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth. The power-up detect circuit includes comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; and monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at X*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(X*Vpth).

Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A.

Abstract: A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.