Abstract: A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Abstract: A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Abstract: Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. A low film resistance results from the great penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against “latch-up”, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance.

Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region.

Abstract: A microcooling device and a method for its manufacture. The microcooling device has a high heat conductivity, is designed to accommodate electronic components on its exterior surface, and has a channel structure in its interior through which a coolant fluid can flow to carry heat away from the components. The channel structure is formed by a base substrate provided with a plurality of recesses and a cover layer externally covering the recesses, the cover layer being made from an electrically insulating and heat-conducting material, and being such that the electronic components can be mounted directly thereon.

Abstract: The invention relates to a composite structure for an electronic component with an undoped diamond layer, at least one side of which is covered by a doped non-diamond layer, arranged on a growth substrate. The diamond layer has a thickness of less than 0.5 .mu.m. In addition, the conduction and/or valence bands of the diamond layer and the nondiamond layer exhibit such a band discontinuity that charge carries from the doped non-diamond layer which are excited optically and/or thermally, for example, can be drawn, with a reduction of their potential energy, into the valence and/or conduction band of the undoped diamond layer. This configuration causes a potential well to exist in the area of the diamond layer, at least in one direction, with a quantizing effect for the charge carriers drawn into the diamond layer.

Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region.

Abstract: A composite structure for electronic components, having a base substrate with a flat side provided with a depression, and having a cover layer which is disposed on the flat side structured by the depression, and the depression being covered to form a hollow structure. The depression in the base substrate is created prior to the deposition of the cover layer and has a clear width measured parallel to the flat side that is less than one-half of its clear depth measured before the cover layer is applied. The vapor phase deposited cover layer is formed from a material which has a sufficiently high surface tension to promote three-dimensional growth of the vapor phase deposited layer.

Abstract: The invention provides a composite structure for microelectronic components having a self-supporting metal plate, an electrically insulating layer adhering to the metal plate, and a functional layer adhering to the insulating layer for the application of at least one microelectronic component. An at least largely monocrystalline information layer which covers the metal plate at points is applied to the self-supporting metal plate. The regions of the surface of the metal plate which are free of the information layer are provided with the insulating layer. When the surface of the information layer is exposed at least in regions, the functional layer is deposited on the insulating layer and on the exposed information layer. The crystal information required for an epitaxial deposition of the functional layer is taken from the information layer.

Abstract: The invention relates to a composite structure including a semiconductor layer arranged on a diamond layer and/or a diamond-like layer, for subsequent processing to produce electronic components and/or groups of components and to a process for producing such a composite structure. In order to improve the quality of the subsequent components, the diamond layer is deposited underneath the component source zones from which the components are subsequently produced, and the diamond or diamond-like layer is provided at the margins of the component source zones and/or outside of the component source zones with edges where the thickness of the layer changes abruptly such that the edges have an edge height amounting to at least 1O%, preferably at least 50%, of the layer thickness of the diamond layer.

Abstract: The invention relates to a composite structure for electronic components comprising a growth substrate, an intermediate layer having substantially a crystallographic lattice structure arranged on the growth substrate, and a diamond layer applied on top of the intermediate layer, and to a process for producing a composite structure of this type. In order to obtain a diamond layer of highest quality, the intermediate layer has substantially a zinc blende or diamond or a calcium fluoride structure, in which at the outset of the intermediate layer the difference between the lattice constant of the intermediate layer and the lattice constant of the growth substrate, relative to the lattice constant of the growth substrate, is less than 20%, in particular less than 10%, and in which at the transition from the intermediate layer to the diamond layer for the lattice constant of the intermediate layer and the lattice constant of the diamond layer the value of the expression .vertline.(n*a.sub.ZS -m*a.sub.D).vertline.

Abstract: An arrangement of a plurality of microcooling devices provided with electrical components, each microcooling device having a closed channel structure for a coolant to flow through, and being provided with electrical conductors for the electronic components and with externally carried fluid ducts for a coolant which flows through the channel structures. A covering layer which forms one of at least two flat sides of the microcooling device is made from an electrically insulating material with good heat conductivity. The electronic components are arrayed on this cover layer and on the opposite flat side of each microcooling device. Adjacent microcooling devices which are provided with electronic components on confronting flat sides are arranged with their components spaced apart or staggered with respect to one another, and the components of one microcooling device preferably are in contact with the cover layer of the adjacent microcooling device.

Abstract: The invention relates to a semiconductor composite structure for an electronic component. The semiconductor composite structure comprises a diamond layer, which is substantially undoped except for unavoidable impurities, one side of which is covered by a doped diamond-free semiconductor layer, with the layers being arranged on a growth substrate. The discontinuity which exists at the transition between the semiconductor layer and the diamond layer with respect to the conduction band and/or the valence band, is such that in the semiconductor layer charge carriers, which are excited optically and/or thermally, can be conducted in the valence band and/or conduction band of the undoped diamond layer with a decrease in their potential energy.

Abstract: The invention relates to a composite structure for electronic components comprising a growth substrate, an intermediate layer having substantially a crystallographic lattice structure arranged on the growth substrate, and a diamond layer applied on top of the intermediate layer, and to a process for producing a composite structure of this type. In order to obtain a diamond layer of highest quality, the intermediate layer has substantially a zinc blende or diamond or a calcium fluoride structure, in which at the outset of the intermediate layer the difference between the lattice constant of the intermediate layer and the lattice constant of the growth substrate, relative to the lattice constant of the growth substrate, is less than 20%, in particular less than 10%, and in which at the transition from the intermediate layer to the diamond layer for the lattice constant of the intermediate layer and the lattice constant of the diamond layer the value of the expression.vertline.(n*a.sub.ZS -m*a.sub.D).vertline.