Patents by Inventor Tim H. Bossart
Tim H. Bossart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811355Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: November 27, 2018Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Patent number: 10388601Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: December 14, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20190103350Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: ApplicationFiled: November 27, 2018Publication date: April 4, 2019Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20180114751Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Patent number: 9911693Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: August 28, 2015Date of Patent: March 6, 2018Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20170062324Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Patent number: 8658336Abstract: Some embodiments include methods for correcting for variation across substrates. A difference map is created to indicate differences between a desired pattern that is to be formed across the substrates utilizing photolithographic processing and a signature pattern representing the actual pattern formed with an initial setting of illumination optics. Modifications to the illumination optics are determined for improving problematic regions identified in the difference map, and the illumination optics are then modified. Substrates are photolithographically processed utilizing the modified illumination optics.Type: GrantFiled: April 30, 2012Date of Patent: February 25, 2014Assignee: Micron Technology, Inc.Inventors: Yuan He, Scott L. Light, Tim H. Bossart
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Publication number: 20130288167Abstract: Some embodiments include methods for correcting for variation across substrates. A difference map is created to indicate differences between a desired pattern that is to be formed across the substrates utilizing photolithographic processing and a signature pattern representing the actual pattern formed with an initial setting of illumination optics. Modifications to the illumination optics are determined for improving problematic regions identified in the difference map, and the illumination optics are then modified. Substrates are photolithographically processed utilizing the modified illumination optics.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Yuan He, Scott L. Light, Tim H. Bossart
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Patent number: 6914017Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.Type: GrantFiled: August 30, 2000Date of Patent: July 5, 2005Assignee: Micron Technology, Inc.Inventors: Pary Baluswamy, Scott J. DeBoer, Ceredig Roberts, Tim H. Bossart
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Patent number: 6822342Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.Type: GrantFiled: November 28, 2001Date of Patent: November 23, 2004Assignee: Micron Technology, Inc.Inventors: Pary Baluswamy, Scott J. DeBoer, Ceredig Roberts, Tim H. Bossart
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Patent number: 6675053Abstract: In the manufacture of a multi-layer integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer's dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.Type: GrantFiled: September 11, 2002Date of Patent: January 6, 2004Assignee: Micron Technology, Inc.Inventors: Pary Baluswamy, Tim H. Bossart
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Publication number: 20030027368Abstract: In the manufacture of a multi-layer integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer's dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.Type: ApplicationFiled: September 11, 2002Publication date: February 6, 2003Inventors: Pary Baluswamy, Tim H. Bossart
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Patent number: 6484060Abstract: In the manufacture of a multi-lay integrated circuit, a reference target is etched into a test wafer along with circuit features of a reference layer. As successive dependent layers are printed, successive dependent targets overlaying the same reference target are formed in photoresist. As each successive dependent target is printed, the degree to which it is registered with the reference target is used to determine the overlay error. After determination of overlay error for a layer, the layer's dependent target is removed, allowing the reference target to be matched with the dependent target of another layer.Type: GrantFiled: March 24, 2000Date of Patent: November 19, 2002Assignee: Micron Technology, Inc.Inventors: Pary Baluswamy, Tim H. Bossart
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Publication number: 20020036332Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.Type: ApplicationFiled: November 28, 2001Publication date: March 28, 2002Inventors: Pary Baluswamy, Scott J. DeBoer, Ceredig Roberts, Tim H. Bossart