Patents by Inventor Tim Hsiao

Tim Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150279832
    Abstract: A compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A SiN protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.
    Type: Application
    Filed: May 27, 2015
    Publication date: October 1, 2015
    Inventors: Shinichiro TAKATANI, Tim HSIAO
  • Publication number: 20130052817
    Abstract: A method for fabrication of bonding solder layers on metal bumps with improved coplanarity, applicable to the flip-chip bump bonding technique for semiconductor IC packaging. When metal bumps have different sizes, the bonding solders thereon may have different heights after high-temperature reflows. The present invention can improve the coplanarity of bonding solders, and mitigating or even eliminating the difficulties in downstream packaging and testing caused by the inconsistent height of bonding solders. To achieve this purpose, the present invention proposes a two-step fabrication method for controlling the surface areas of the metal bumps and the bonding solder layers thereon separately, and thereby improving the coplanarity of the bonding solders after high-temperature reflows. The two-step fabrication method includes: a first-step process for forming metal bumps on the semiconductor devices; and a second-step process for forming bonding solder layers of different sizes on the metal bumps.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventor: Tim Hsiao
  • Publication number: 20100101640
    Abstract: An optical structure is characterized by improving a primary lens of a photovoltaic concentrator system. The optical structure is accomplished by properly dividing the primary lens, determining required optical operational regions, and arranging the optical operational regions basing on an identical location into an annular array, thereby forming the complete optical structure. The optical structure facilitates enhancing uniformity of light distribution throughout the optical operational regions, improving photoelectric conversion efficiency of a solar cell having the optical structure, and reducing operational distance between the primary lens and the solar cell.
    Type: Application
    Filed: April 6, 2009
    Publication date: April 29, 2010
    Inventors: Jain-Cheng Chen, Chung-Ying Wu, Hsiung-Yu Tsai, Wen-Chun Yeh, Chen-Hsiang Hsu, Tim Hsiao, Shih-Chi Chien
  • Publication number: 20060065571
    Abstract: A wafer shipping box for carrying a number of wafers is provided. The wafer shipping box includes a main body, a cover and a sealing element. The cover can join up with the main body to seal off wafers inside the wafer shipping box. A vent hole is set up on either the body or the cover. The sealing element is used to seal or open the vent hole. Through the sealing element, the vent hole can be sealed so that micro-particles and corrosive gases are prevented from contaminating the wafers and the interior of the wafer box during shipment.
    Type: Application
    Filed: September 27, 2004
    Publication date: March 30, 2006
    Inventors: Tim Hsiao, Jason Horng