Patents by Inventor Tim J. Buick

Tim J. Buick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processor coupled to a sequencer circuit that provides efficient scalable queuing and method
    Patent number: 8156265
    Abstract: A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tim J. Buick, John F. Pillar
  • Data Processor with Efficient Scalable Queuing and Method Therefor
    Publication number: 20100306483
    Abstract: A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 2, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tim J. Buick, John F. Pillar