Patents by Inventor Tim J. Corbett
Tim J. Corbett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9039474Abstract: Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices.Type: GrantFiled: November 11, 2011Date of Patent: May 26, 2015Assignee: Micron Technology, Inc.Inventors: Sameer S. Vadhavkar, Tim J. Corbett, Xiao Li
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Publication number: 20130119419Abstract: Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Sameer S. Vadhavkar, Tim J. Corbett, Xiao Li
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Patent number: 7511520Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: August 20, 2007Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett, Warren M. Farnworth
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Patent number: 7452732Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser-reactive marking material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser-reactive marking material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.Type: GrantFiled: May 19, 2003Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventor: Tim J. Corbett
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Patent number: 7362113Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: December 5, 2001Date of Patent: April 22, 2008Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7288953Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: March 12, 2004Date of Patent: October 30, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7167012Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: April 21, 2003Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7167014Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: June 30, 2005Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7161373Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: June 30, 2005Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7141997Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: June 30, 2005Date of Patent: November 28, 2006Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7112986Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: June 30, 2005Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 7112985Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: June 30, 2005Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 6998860Abstract: A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.Type: GrantFiled: July 10, 2000Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Chender Huang, Larry D. Kinsman
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Publication number: 20040212391Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: ApplicationFiled: March 12, 2004Publication date: October 28, 2004Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 6770906Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.Type: GrantFiled: February 19, 2003Date of Patent: August 3, 2004Assignee: Micron Technology, Inc.Inventors: Tim J. Corbett, Raymond P. Scholer, Fernando Gonzalez
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Patent number: 6737882Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: GrantFiled: December 11, 2002Date of Patent: May 18, 2004Assignee: Micron Technology, Inc.Inventors: Alan G. Wood, Tim J. Corbett
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Patent number: 6683637Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser reactive material, such as a pigment containing epoxy is present. The heat associated with the laser beam causes the laser reactive material to fuse to the surface of the chip creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface, and the remaining residue on the non-irradiated portion can be readily removed.Type: GrantFiled: May 23, 2002Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventor: Tim J. Corbett
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Publication number: 20030206030Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.Type: ApplicationFiled: April 21, 2003Publication date: November 6, 2003Inventors: Alan G. Wood, Tim J. Corbett
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Publication number: 20030203591Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser reactive material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser reactive material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.Type: ApplicationFiled: May 19, 2003Publication date: October 30, 2003Inventor: Tim J. Corbett
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Publication number: 20030151047Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.Type: ApplicationFiled: February 19, 2003Publication date: August 14, 2003Inventors: Tim J. Corbett, Raymond P. Scholer, Fernando Gonzalez