Patents by Inventor Tim J. Corbett

Tim J. Corbett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9039474
    Abstract: Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Tim J. Corbett, Xiao Li
  • Publication number: 20130119419
    Abstract: Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sameer S. Vadhavkar, Tim J. Corbett, Xiao Li
  • Patent number: 7511520
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: March 31, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett, Warren M. Farnworth
  • Patent number: 7452732
    Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser-reactive marking material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser-reactive marking material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: November 18, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Tim J. Corbett
  • Patent number: 7362113
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: April 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7288953
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7167012
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7167014
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7161373
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7141997
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7112986
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7112985
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 6998860
    Abstract: A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: February 14, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Chender Huang, Larry D. Kinsman
  • Publication number: 20040212391
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Application
    Filed: March 12, 2004
    Publication date: October 28, 2004
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 6770906
    Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 3, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tim J. Corbett, Raymond P. Scholer, Fernando Gonzalez
  • Patent number: 6737882
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: May 18, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 6683637
    Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser reactive material, such as a pigment containing epoxy is present. The heat associated with the laser beam causes the laser reactive material to fuse to the surface of the chip creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface, and the remaining residue on the non-irradiated portion can be readily removed.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Tim J. Corbett
  • Publication number: 20030206030
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Application
    Filed: April 21, 2003
    Publication date: November 6, 2003
    Inventors: Alan G. Wood, Tim J. Corbett
  • Publication number: 20030203591
    Abstract: A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser reactive material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser reactive material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.
    Type: Application
    Filed: May 19, 2003
    Publication date: October 30, 2003
    Inventor: Tim J. Corbett
  • Publication number: 20030151047
    Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 14, 2003
    Inventors: Tim J. Corbett, Raymond P. Scholer, Fernando Gonzalez