Patents by Inventor Tim J. Edwards

Tim J. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5790415
    Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409).
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: August 4, 1998
    Inventors: Satyamurthy Pullela, Abhijit Dharchoudhury, David T. Blaauw, Tim J. Edwards, Joseph W. Norton
  • Patent number: 5787008
    Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409).
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: July 28, 1998
    Assignee: Motorola, Inc.
    Inventors: Satyamurthy Pullela, Abhijit Dharchoudhury, David T. Blaauw, Tim J. Edwards, Joseph W. Norton, Peter R. O'Brien
  • Patent number: 5751593
    Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409).
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventors: Satyamurthy Pullela, Abhijit Dharchoudhury, David T. Blaauw, Tim J. Edwards, Joseph W. Norton
  • Patent number: 5506728
    Abstract: A combiner eyepiece with an enhancement imagery source and a collimating mirror is equipped with two oblique partially reflective mirrors. Both mirrors reflect some of the light impinging on their partially reflective sides and transmit substantially all of the rest of such light. The result is a collimated beam of light travelling toward the viewer along the viewing axis and expanded in vertical extent. This expanded vertical extent eases the requirement for the viewer to place his eyes in a precise location at the near end of the eyepiece. It also allows a smaller and lighter construction for an eyepiece where the vertical extent of the viewing area has been specified.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: April 9, 1996
    Assignee: Kaiser Aerospace & Electronics Corporation
    Inventors: Tim J. Edwards, Mayer Rud