Patents by Inventor Tim J. WILKENS

Tim J. WILKENS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
    Patent number: 11023241
    Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 1, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrej Kocev, Jay Fleischman, Kai Troester, Johnny C. Chu, Tim J. Wilkens, Neil Marketkar, Michael W. Long
  • SYSTEMS AND METHODS FOR SELECTIVELY BYPASSING ADDRESS-GENERATION HARDWARE IN PROCESSOR INSTRUCTION PIPELINES
    Publication number: 20200065108
    Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: ANDREJ KOCEV, JAY FLEISCHMAN, KAI TROESTER, JOHNNY C. CHU, TIM J. WILKENS, NEIL MARKETKAR, MICHAEL W. LONG
  • Creating multiple versions for interior pointers and alignment of an array
    Patent number: 8555030
    Abstract: A device identifies array accesses of variables in a program code that includes multiple arrays, and identifies array access patterns for one of the array accesses. The device also determines an order of the array access patterns identified for the array accesses, and calculates, based on the order, distances between the array access patterns. The device further shares address calculations amongst the array accesses associated with array access patterns with one or more of the distances that are equivalent.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tim J. Wilkens, Michael C. Berg
  • CREATING MULTIPLE VERSIONS FOR INTERIOR POINTERS AND ALIGNMENT OF AN ARRAY
    Publication number: 20130019060
    Abstract: A device identifies array accesses of variables in a program code that includes multiple arrays, and identifies array access patterns for one of the array accesses. The device also determines an order of the array access patterns identified for the array accesses, and calculates, based on the order, distances between the array access patterns. The device further shares address calculations amongst the array accesses associated with array access patterns with one or more of the distances that are equivalent.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 17, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Tim J. WILKENS, Michael C. BERG