Patents by Inventor Tim Kubera

Tim Kubera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11837672
    Abstract: A stacked multijunction solar cell having a dielectric insulating layer system, a germanium substrate, which forms an underside of the multijunction solar cell, a germanium subcell and at least two III-V subcells, which follow each other in the specified order, the insulating layer system includes a layer sequence made up of at least one bottom insulating layer, which is integrally connected to a first surface section of the multijunction solar cell and a top insulating layer forming an upper side of the insulating layer system, and a metal coating of the multijunction solar cell is integrally and electrically conductively connected to a second surface section abutting the first surface section of the multijunction solar cell and is integrally connected to a section of the upper side of the insulating layer system, and the top insulating layer comprises amorphous silicon or is made up of amorphous silicon.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 5, 2023
    Assignee: AZUR SPACE Solar Power GmbH
    Inventors: Tim Kubera, Bianca Fuhrmann
  • Publication number: 20220310854
    Abstract: A solar cell contact arrangement, having a semiconductor body with a top and a bottom, wherein the semiconductor body has multiple solar cell stacks and includes a support substrate on the bottom, and each solar cell stack has at least two III-V subcells arranged on the support substrate and at least one through-contact extending from the top to the bottom of the semiconductor body with a continuous side wall, wherein the through-contact has a first edge region on the top and a second edge region on the bottom, and the first edge region has a first section and a second, metallic section, and the second edge region has a first section and a second section, wherein the respective second sections completely enclose the respective first sections, and an insulating layer.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 29, 2022
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Wolfgang KOESTLER, Tim KUBERA
  • Publication number: 20220285567
    Abstract: A method for plating by means of a through-hole on a semiconductor wafer at least comprising the steps: providing a semiconductor wafer having a top side and a bottom side, wherein the semiconductor wafer has a plurality of solar cell stacks and comprises a substrate on the bottom side, and each solar cell stack has at least two III-V subcells, disposed on the substrate, and at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall, wherein the through-hole has a first edge region on the top side and a second edge region on the bottom side; applying an insulating layer to part of the first edge region, the side wall, and to the second edge region by means of a first printing process; and applying an electrically conductive layer.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 8, 2022
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Wolfgang KOESTLER, Tim KUBERA
  • Publication number: 20210066516
    Abstract: A stacked multijunction solar cell having a dielectric insulating layer system, a germanium substrate, which forms an underside of the multijunction solar cell, a germanium subcell and at least two III-V subcells, which follow each other in the specified order, the insulating layer system includes a layer sequence made up of at least one bottom insulating layer, which is integrally connected to a first surface section of the multijunction solar cell and a top insulating layer forming an upper side of the insulating layer system, and a metal coating of the multijunction solar cell is integrally and electrically conductively connected to a second surface section abutting the first surface section of the multijunction solar cell and is integrally connected to a section of the upper side of the insulating layer system, and the top insulating layer comprises amorphous silicon or is made up of amorphous silicon.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 4, 2021
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Tim KUBERA, Bianca Fuhrmann
  • Patent number: 10170311
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Publication number: 20170271159
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Patent number: 9679772
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: June 13, 2017
    Assignees: International Business Machines Corporation, AZUR SPACE SOLAR POWER GMBH
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Publication number: 20170110320
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Publication number: 20110139241
    Abstract: A solar cell and to a method for producing a solar cell is provided. The solar cell includes a semi-conductor substrate with doped regions (2a, 2b). Contact structures (3b, 3c) which are connected to the doped regions (2a, 2b) and connecting structures (4a, 4b) which are superimposed are arranged on one side of the semi-conductor substrate. The connecting structures (4a, 4b) are connected to the contact structures (3b, 3c) through openings (9) in an intermediate insulating layer (5).
    Type: Application
    Filed: July 10, 2009
    Publication date: June 16, 2011
    Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Florian Clement, Daniel Biro, Michael Menko (born Lutsch), Tim Kubera