Patents by Inventor Tim Lambert

Tim Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160274798
    Abstract: Systems and methods for management of scalable storage architectures are disclosed. The system includes one or more storage backplanes, each storage backplane configured to interface with one or more hard disk drives. The system includes a baseboard management controller, which includes an interface to communicate with one or more of the storage backplanes and programmable logic configured to detect the presence of one or more hard disk drives in an interfaced storage backplane and control one or more status indicators, wherein each status indicator is related to at least one of the hard disk drives in the interfaced storage backplane.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Shawn Joel Dube, Tim Lambert, Surender V. Brahmaroutu
  • Publication number: 20160233729
    Abstract: To reduce stray magnetic fields and the accompanying inefficiency in electric motors, the present specification provides a motor having a plurality of stator poles and rotor poles. The rotor poles are configured to rotate across the stator poles. Each of the rotor poles has a first rotor pole component and a second rotor pole component disposed on opposite sides of the plurality of stator poles. Each of the stator poles comprises at least a first sub-pole and a second sub-pole arranged such that at least a portion of magnetic flux from the first sub-pole flows through the first rotor pole component, through the second sub-pole, through the second rotor pole component and back through the first subpole. As the rotor poles rotate with respect to the stator poles, the magnetic flux exerts a rotating force on the plurality of rotor poles.
    Type: Application
    Filed: September 19, 2014
    Publication date: August 11, 2016
    Inventor: Tim LAMBERT
  • Patent number: 6374377
    Abstract: A processor includes a plurality of I/O connectors and an embedded memory array having a plurality of memory cells and a plurality of bitlines coupled to the plurality of memory cells. The processor also includes low yield analysis circuitry, coupled to both the embedded memory array and a first connector of the plurality of I/O connectors, to provide a coupling between a portion of the embedded memory array and the first connector.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: April 16, 2002
    Assignee: Intel Corporation
    Inventors: Douglas A. Guddat, Glenn F. King, Tim Lambert
  • Patent number: 6366990
    Abstract: A method and apparatus for software controlled timing of embedded memory includes an embedded memory array and input/output (I/O) control circuitry coupled to the embedded memory array. The I/O control circuitry provides a plurality of I/O signals to the embedded memory array to control the input of data to the embedded memory array and output of data from the embedded memory array. The I/O control circuitry also includes programmable delay circuitry to alter the timing of the I/O signals.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Douglas A. Guddat, Glenn F. King, Tim Lambert, Navin Saxena, Peter J. DesRosier