Abstract: Certain embodiments of present disclosure provide a high voltage (e.g., 3.3V) tolerant MOS gate unit implemented using low voltage (e.g., 1.8V) MOS transistors. The MOS gate unit comprises source, drain and gate terminals, and first, second and third transistors each configured to operate at a lower voltage (e.g., 1.8V). The first transistor has its source coupled to the source terminal and its drain coupled to the source of the second transistor. The third transistor has its source (or drain) coupled to the gate of the first transistor, its drain (or source) coupled to the gate terminal, and its gate coupled to the gate of the second transistor. The second transistor has its drain coupled to the drain terminal. The MOS gate unit functions the same as a MOS transistor configured to operate at a higher voltage (e.g., 3.3V) when a limiting voltage (e.g., 1.65V) significantly lower than the higher voltage is applied to the gate of the third transistor.

Abstract: Certain embodiments of present disclosure provide a voltage detector including input gates configured to receive an input voltage and a reference voltage, and input devices and protection devices each having a low threshold voltage. The voltage detector further includes a current source, first and second diode-connected loads, first and second pre-charging devices, and an input differential amplifier made of devices having threshold voltages significantly higher than the low threshold voltages. The voltage detector is operable with a supply voltage about twice as high as an upper limit of an operating voltage range for the input devices. The voltage detector in an “ON” state is configured to drive an output voltage at the output of the differential amplifier higher or lower in response to the input voltage being driven above or below the reference voltage, respectively. Also provided herein is a voltage regulator including the voltage detector.

Abstract: A resistive-type memory device comprises at least one memory array. Each memory array includes reference cells and a reference generator that generates a reference voltage that is midway between a first voltage and a second voltage, the first voltage being a function of a first current through a first reference cell, the second voltage being a function of a second current through a second reference cell, the first reference cell and the second reference cell being a pair of reference cells storing complementary values in a row of the memory array. The reference voltage is thus automatically centered and tracks the variation in a read current for all PVT corners without the need of tuning and adjustment of the reference voltage. This reference generator works with a current sense amplifier in certain implementation examples to reliably output the correct read data for all PVT corners.

Abstract: A non-volatile static random-access memory (NVSRAM) device includes at least one array of NVSRAM cells. Each NVSRAM cell includes an SRAM unit and an MRAM unit. The SRAM unit includes at least six transistors, and the MRAM unit includes at least two-transistors and two magnetic tunnel junction (MTJ) structures. The SRAM units are accessed during normal read/write operations to allows for fast access to the NVSRAM cells with unlimited endurance and without read/write error rate issues. Hidden MRAM write operations in NVSRAM cells that are not accessed for normal read/write operations may be activated manually or automatically to back up the data stored in the corresponding SRAM units. When the NVSRAM device loses power, data stored in the SRAM units are lost, while the data backed-up in corresponding MRAM units are retained. When power is restored, an automatic data restore write cycle is started, during which the SRAM units recover their data from their corresponding MRAM units.

Abstract: A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device; and bonding pads. The bonding pads are connected to inputs of the option selection logic. The bonding pads are configurable to allow for a default mode selection for the selected one of the plurality of memory configuration modes to operate the memory device.

Abstract: A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device; and bonding pads. The bonding pads are connected to inputs of the option selection logic. The bonding pads are configurable to allow for a default mode selection for the selected one of the plurality of memory configuration modes to operate the memory device.

Abstract: A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.

Abstract: One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Abstract: A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

Abstract: An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

Abstract: An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.

Abstract: The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.