Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A software implementation of an application watchdog, comprising a restart service operating in the user mode and a watchdog driver operating in the kernel mode of a computer operating system. The driver incorporates a system thread configured to monitor a plurality of user applications operating in the user mode. The driver provides a first IOCTL signal interface for communicating control signals between the watchdog driver and one of the user applications and a second IOCTL signal interface for communicating control signals between the watchdog driver and the restart service. A communication interface exists for coordinating timer events with the operating system scheduler. If the system thread does not receive a message from one of said applications within an allotted period of time, the timer event alerts the watchdog driver that the allotted time has elapsed and the watchdog driver signals the restart service to restart that application.

Abstract: A system and technique for detecting and classifying data errors in a memory device. More specifically, data errors in a memory device are detected by a host controller. The error is classified as a hard error or a soft error. If the error is classified as a hard error, a tracking device is implemented to track the number of hard errors detected in the system. Once a pre-determined number of hard errors are detected in a particular memory segment, an indicator, such as a light emitting diode (LED), may be used to indicate the corresponding memory segment should be replaced.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Abstract: A system and technique for detecting and classifying data errors in a memory device. More specifically, hard and soft data errors in a memory device are detected by initiating a READ request initiated from a host controller. If an error is detected, the data is corrected and re-written to the corresponding memory location. A second READ request is then issued to read the corrected data. If a second error is detected in the corrected data, the error is classified as a hard error and a counter is incremented to track the number of hard errors detected in the system Once a programmable threshold number of hard errors are detected in a particular memory segment, an indicator, such as a light emitting diode (LED), is used to indicate that the corresponding memory segment should be replaced.