Patents by Inventor Tim Parker
Tim Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240077552Abstract: Systems and methods are disclosed for increasing a nuclear spin polarization of a target compound. In accordance with such systems and methods, a first non-thermal equilibrium nuclear spin polarization can be imparted to at least one source atom of a source compound, the source atom having a nuclear gyromagnetic ratio of at least 12 megahertz per tesla (MHz/T). A first solution can be obtained that includes the source compound and a target compound. The at least one source atom can be present in a source concentration of at least 0.1 molar (M) in the first solution. A second non-thermal equilibrium nuclear spin polarization of at least 0.01% can be imparted to the at least one target atom of the target compound via a nuclear Overhauser effect (NOE) transfer of the first non-thermal equilibrium nuclear spin polarization to the at least one target atom.Type: ApplicationFiled: July 27, 2023Publication date: March 7, 2024Applicant: NVISION IMAGING TECHNOLOGIES GMBHInventors: Ilai SCHWARTZ, Anna PARKER, Stephan KNECHT, Tim EICHHORN, John BLANCHARD
-
Patent number: 10552523Abstract: In some embodiments, a system for automatically identifying synonyms within a token-based data management system includes a database configured to store a plurality of records, and a computing device having a synonym locator configured to create a token synonym mapping by automatically identifying token synonyms within the plurality of records based on a statistical analysis of the plurality of records. The token synonym mapping includes a first token linked to a second token, where the second token is a valid synonym of the first token. The computing device includes a synonym standardizer configured to standardize at least one record of the plurality of records based on the token synonym mapping such that, when the at least one record includes the second token, the synonym standardizer is configured to automatically replace the second token with the first token.Type: GrantFiled: October 14, 2016Date of Patent: February 4, 2020Assignee: SAP SEInventors: Jim Havlicek, Tim Parker
-
Patent number: 10191942Abstract: A token-based database management system described herein may reduce an amount of comparisons during entity resolution of records. The system includes a token creator configured to create tokens from records, a token-record mapping creator configured to create a token-record mapping of tokens to records, a token importance calculator configured to calculate token importance values for the tokens, a token pruner configured to identify a token of the current record as unimportant based on token importance values of the tokens of the current record, and to remove the unimportant token from the token-record mapping, a record selector configured to select only records sharing at least one common token with the current record, and a record comparator configured to compare the current record with each of the selected records to determine whether the current record matches any of the selected records.Type: GrantFiled: October 14, 2016Date of Patent: January 29, 2019Assignee: SAP SEInventors: Tim Parker, Jim Havlicek
-
Publication number: 20180107730Abstract: A token-based database management system described herein may reduce an amount of comparisons during entity resolution of records. The system includes a token creator configured to create tokens from records, a token-record mapping creator configured to create a token-record mapping of tokens to records, a token importance calculator configured to calculate token importance values for the tokens, a token pruner configured to identify a token of the current record as unimportant based on token importance values of the tokens of the current record, and to remove the unimportant token from the token-record mapping, a record selector configured to select only records sharing at least one common token with the current record, and a record comparator configured to compare the current record with each of the selected records to determine whether the current record matches any of the selected records.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Tim Parker, Jim Havlicek
-
Publication number: 20180107702Abstract: In some embodiments, a system for automatically identifying synonyms within a token-based data management system includes a database configured to store a plurality of records, and a computing device having a synonym locator configured to create a token synonym mapping by automatically identifying token synonyms within the plurality of records based on a statistical analysis of the plurality of records. The token synonym mapping includes a first token linked to a second token, where the second token is a valid synonym of the first token. The computing device includes a synonym standardizer configured to standardize at least one record of the plurality of records based on the token synonym mapping such that, when the at least one record includes the second token, the synonym standardizer is configured to automatically replace the second token with the first token.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Jim Havlicek, Tim Parker
-
Patent number: 8966425Abstract: A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.Type: GrantFiled: March 14, 2013Date of Patent: February 24, 2015Assignee: Pulsic LimitedInventors: Robert Eisenstadt, Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
-
Patent number: 8788999Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: July 2, 2013Date of Patent: July 22, 2014Assignee: Pulsic LimitedInventors: Graham Baldsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
-
Patent number: 8751996Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: December 11, 2012Date of Patent: June 10, 2014Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
-
Patent number: 8479139Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: July 9, 2010Date of Patent: July 2, 2013Assignee: Pulsic LimitedInventors: Graham Baldsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
-
Patent number: 8479141Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: January 17, 2012Date of Patent: July 2, 2013Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
-
Patent number: 8376815Abstract: A method of tenderizing meat on a poultry carcass includes defeathering the poultry carcass, and subsequently applying a pulsed electrical voltage across the poultry carcass. The electrical voltage can be sufficient to impart an electrical current across the poultry carcass that is at least about 350 milliamps. An apparatus for tenderizing meat on a poultry carcass is also discussed.Type: GrantFiled: April 30, 2009Date of Patent: February 19, 2013Assignee: Perdue Holdings, Inc.Inventor: Tim Parker
-
Patent number: 8332805Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: July 11, 2011Date of Patent: December 11, 2012Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
-
Patent number: 8304441Abstract: The present invention relates to thiazolidinedione analogues that are useful for treating hypertension, diabetes, and inflammatory diseases.Type: GrantFiled: November 16, 2011Date of Patent: November 6, 2012Assignee: Metabolic Solutions Development Company, LLCInventors: Gerard R. Colca, Robert C. Gadwood, Tim Parker
-
Publication number: 20120129896Abstract: The present invention relates to thiazolidinedione analogues that are useful for treating hypertension, diabetes, and inflammatory diseases.Type: ApplicationFiled: November 16, 2011Publication date: May 24, 2012Applicant: Metabolic Solutions Development CompanyInventors: Gerard R. Colca, Robert C. Gadwood, Tim Parker
-
Patent number: 8171447Abstract: A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.Type: GrantFiled: March 20, 2009Date of Patent: May 1, 2012Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
-
Patent number: 8099700Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: January 17, 2012Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
-
Patent number: 8067450Abstract: The present invention relates to thiazolidinedione analogues that are useful for treating hypertension, diabetes, and inflammatory diseases. Formula (I), wherein: each of R1 and R4 is independently selected from H, halo, aliphatic, and alkoxy, wherein the aliphatic and alkoxy are optionally substituted with 1-3 of halo; R2 is halo, hydroxy, or optionally substituted aliphatic, and R?2 is H, or R2 and R?2 together form oxo; R3 is H; and Ring A is a phenyl.Type: GrantFiled: September 15, 2008Date of Patent: November 29, 2011Assignee: Metabolic Solutions Development CompanyInventors: Gerard R. Colca, Robert C. Gadwood, Tim Parker
-
Patent number: 8010928Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: March 14, 2008Date of Patent: August 30, 2011Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
-
Patent number: 7823113Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: September 11, 2006Date of Patent: October 26, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
-
Patent number: 7802208Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: September 21, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato