Patents by Inventor Tim S. Michels

Tim S. Michels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9606946
    Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 28, 2017
    Assignee: F5 Networks, Inc.
    Inventor: Tim S. Michels
  • Patent number: 9313047
    Abstract: Handling network data packets classified as being high throughput and low latency with a network traffic management device is disclosed. Packets are received from a network and classified as high throughput or low latency based on packet characteristics or other factors. Low latency classified packets are generally processed immediately, such as upon receipt, while the low latency packet processing is strategically interrupted to enable processing coalesced high throughput classified packets in an optimized manner. The determination to cease processing low latency packets in favor of high throughput packets may be based on a number of factors, including whether a threshold number of high throughput classified packets are received or based on periodically polling a high throughput packet memory storage location.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 12, 2016
    Assignee: F5 Networks, Inc.
    Inventors: Tim S. Michels, Dave Schmitt, Paul I. Szabo
  • Publication number: 20150149681
    Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 28, 2015
    Inventor: Tim S. Michels
  • Publication number: 20150049763
    Abstract: Handling network data packets classified as being high throughput and low latency with a network traffic management device is disclosed. Packets are received from a network and classified as high throughput or low latency based on packet characteristics or other factors. Low latency classified packets are generally processed immediately, such as upon receipt, while the low latency packet processing is strategically interrupted to enable processing coalesced high throughput classified packets in an optimized manner. The determination to cease processing low latency packets in favor of high throughput packets may be based on a number of factors, including whether a threshold number of high throughput classified packets are received or based on periodically polling a high throughput packet memory storage location.
    Type: Application
    Filed: November 6, 2009
    Publication date: February 19, 2015
    Applicant: F5 Networks, Inc.
    Inventors: Tim S. Michels, Dave Schmitt, Paul I. Szabo
  • Patent number: 8880632
    Abstract: A method and apparatus for handling packets received from a server over a network based upon quality of network service on DMA channels includes inspecting a packet received by a network device, classifying the inspected packet with the network device based on one or more class of service identifiers in the packet, assigning with the network device the classified packet to one of a plurality of DMA rings associated with a DMA channel based on the one or more class of service identifiers in the packet, and moving the assigned packet to a host memory based upon the assigning.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 4, 2014
    Assignee: F5 Networks, Inc.
    Inventor: Tim S. Michels
  • Patent number: 8880696
    Abstract: A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: November 4, 2014
    Assignee: F5 Networks, Inc.
    Inventor: Tim S. Michels