Patents by Inventor Tim Schönauer

Tim Schönauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistive memory and method
    Patent number: 9443583
    Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies AG
    Inventors: Christian Pacha, Tim Schönauer, Michael Kund
  • RESISTIVE MEMORY AND METHOD
    Publication number: 20120026781
    Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 2, 2012
    Applicant: Infineon Technologies AG
    Inventors: Christian Pacha, Tim Schönauer, Michael Kund
  • Resistive memory and method
    Patent number: 8063448
    Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: November 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Christian Pacha, Tim Schönauer, Michael Kund
  • Logic basic cell, logic basic cell arrangement and logic device
    Patent number: 7279936
    Abstract: A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, having four data signal inputs, to which two data signals and the logically complementary data signals thereof can be applied, and having six logic selection elements between the data signal inputs. At a data signal output, the logic combination of the two data signals in accordance with the logic function selected by means of the logic selection elements can be provided as output signal.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: October 9, 2007
    Assignee: Infineon Technologies AG
    Inventors: Jörg Gliese, Tim Schönauer