Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: An integrated circuit is disclosed that measures and/or monitors a substrate parameter. An actual value of the substrate parameter can vary from its expected value as a result of characteristics of the integrated circuit and/or characteristics of an environment surrounding the integrated circuit. The integrated circuit classifies the semiconductor substrate upon which it is fabricated as being a fast semiconductor substrate or a slow semiconductor substrate based upon the substrate parameter. The integrated circuit operates in a fast-substrate mode of operation when the semiconductor substrate is classified as being a fast semiconductor substrate to adjust an operational parameter to compensate for the fast semiconductor substrate or in a slow-substrate mode of operation when the semiconductor substrate is classified as being a slow semiconductor substrate to adjust the operational parameter to compensate for the slow semiconductor substrate.

Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.