Patents by Inventor Tim Tuan

Tim Tuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11443091
    Abstract: An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 13, 2022
    Assignee: Xilinx, Inc.
    Inventors: Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Juan J. Noguera Serra, Goran H. K. Bilski, Jan Langer, Sneha Bhalchandra Date, Stephan Munz, Jose Marques
  • Patent number: 11386020
    Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, Goran Hk Bilski, Juan Jose Noguera Serra, Ismed D. Hartanto, Sridhar Subramanian, Tim Tuan
  • Publication number: 20220197846
    Abstract: An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Patent number: 11336287
    Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 17, 2022
    Assignee: Xilinx, Inc.
    Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
  • Patent number: 11323391
    Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: XILINX, INC.
    Inventors: Peter McColgan, David Clarke, Goran Hk Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan
  • Patent number: 11296707
    Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 5, 2022
    Assignee: Xilinx, Inc.
    Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
  • Publication number: 20220100691
    Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Patent number: 11288222
    Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Tim Tuan, Sridhar Subramanian
  • Patent number: 11223351
    Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 11, 2022
    Assignee: XILINX, INC.
    Inventors: Amarnath Kasibhatla, Saurabh Mathur, Mansi Shrikant Patwardhan, Tim Tuan
  • Patent number: 10866753
    Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 15, 2020
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, David Clarke
  • Patent number: 10747531
    Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 18, 2020
    Assignee: XILINX, INC.
    Inventors: Jan Langer, Baris Ozgul, Juan J. Noguera Serra, Goran HK Bilski, Tim Tuan
  • Patent number: 10635622
    Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 28, 2020
    Assignee: XILINX, INC.
    Inventors: Goran H. K. Bilski, Juan J. Noguera Serra, David Clarke, Tim Tuan, Peter McColgan, Zachary Dickman, Baris Ozgul, Jan Langer
  • Publication number: 20190303033
    Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Goran HK Bilski, Jan Langer, Baris Ozgul, Tim Tuan, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Christopher H. Dick
  • Publication number: 20190303328
    Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Xilinx, Inc.
    Inventors: Goran H.K. Balski, Juan J. Noguera Serra, David Clarke, Tim Tuan, Peter McColgan, Zachary Dickman, Baris Ozgul, Jan Langer
  • Patent number: 9444497
    Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: September 13, 2016
    Assignee: XILINX, INC.
    Inventors: Sundararajarao Mohan, Tim Tuan
  • Patent number: 9355690
    Abstract: A method for asynchronous time multiplexing of information with synchronous interfacing includes, responsive to a first edge of a clock signal, asynchronously loading first data, including first multiple sets of data for multiple operations, into a first asynchronous shift register. The first data is asynchronously unloaded from the first asynchronous shift register to a function block for processing to provide second data, including second multiple sets of data as results of the multiple operations. The second data is asynchronously loaded into a second asynchronous shift register. Responsive to a second edge of the clock signal, the second data is asynchronously unloaded from the second asynchronous shift register as the results of the multiple operations. The first edge and the second edge of the clock signal are associated with a same period of the clock signal.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 31, 2016
    Assignee: XILINX, INC.
    Inventor: Tim Tuan
  • Patent number: 9348959
    Abstract: A method for determining or configuring supply voltage and threshold voltage for a design implementation of a given electronic design, includes: determining a first set of supply voltage-threshold voltage combinations that meet timing requirements for the design implementation; performing power analysis using a processor; and selecting a supply voltage-threshold voltage combination from the first set of supply voltage-threshold voltage combinations based at least in part on a result from the power analysis, wherein the selected supply voltage-threshold voltage combination provides an optimal amount of power consumption for the design implementation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 24, 2016
    Assignee: XILINX, INC.
    Inventor: Tim Tuan
  • Patent number: 9015023
    Abstract: A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 21, 2015
    Assignee: Xilinx, Inc.
    Inventors: Tim Tuan, Daniel Chung, Ronald Cline, Andy DeBaets, Matthew H. Klein
  • Patent number: 8443344
    Abstract: Approaches for generating a hardware definition from a program specified in a high-level language. In one approach, a first set of blocks of instructions in the high-level language program is identified. Each block in the first set is bounded by a respective loop designation in the high-level language. For each block in the first set, an associated respective second set of one or more blocks of the program is identified. Each block in the second set is outside the block in the first set. A hardware definition of the program is generated and stored. For each block in the first set, the hardware definition specifies power-reducing circuitry for one or more blocks in the associated second set. The power-reducing circuitry is controlled based on a status indication from the hardware definition of the block in the first set.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: May 14, 2013
    Assignee: Xilinx, Inc.
    Inventors: Prasanna Sundararajan, Tim Tuan
  • Patent number: 8411527
    Abstract: In a memory device, an array of memory cells is coupled between a virtual ground node and a supply node. First and second transistors are coupled in source-drain parallel between the virtual ground node and a ground bus. The first transistor is substantially larger than the second transistor. A control circuit provides a first gate signal to a gate of the first transistor and a second gate signal to a gate of the second transistor. The control circuit includes: a configuration memory cell providing a first control signal; an interconnect providing a second control signal; and control logic receiving the first and second control signals and providing the first gate signal. The array of memory cells has three modes responsive to the first and second gate signals, where the three modes include an active mode, a first sleep mode, and a second sleep mode.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 2, 2013
    Assignee: Xilix, Inc.
    Inventor: Tim Tuan