Abstract: A protocol analyzer pod for monitoring U-interface data streams in a communication system wherein full duplex U-interface line codes (such as AMI and 2B1Q) are used. The protocol analyzer pod is intrusively inserted (that is, inserted in series) in a U-interface line between a central office and a customer equipment. The protocol analyzer pod includes two cross-connected U-interface transceivers. According to the present invention, each end of the U-interface line is terminated into one of the U-interface transceivers. The two U-interface transceivers perform adaptive equalization and echo cancelling on their respective line segments. Also, the two U-interface transceivers separate the full duplex U-interface data stream on the U-interface line into separate input and output data streams. A protocol analyzer may monitor the full duplex U-interface data stream by monitoring the half duplex input and output data streams.

Abstract: A direct flash converter has independent parallel analog-to-digital encoders for each bit. Cross-coupled level sensors are coupled to a single comparator within each bit encoder to provide a directly encoded Gray code binary output.

Abstract: A dual ramp analog to digital converter which employs a single supply voltage and internal logic circuitry for automatically generating automatic zero and full scale calibration voltages and a virtual second supply voltage of opposite polarity to the single supply voltage for automatically accommodating unknown opposite polarity input voltages to be measured.

Abstract: A four bit binary coded decimal (BCD) up/down counter includes a four bit adder and associated logic circuitry configured to feed therethrough the incoming BCD code words as the actual output for the up count and for the down count, add binary 5 to the incoming BCD code word for 1 through 9 and invert each bit of the resulting code words, and feeding the BCD code word for zero directly to the output.

Abstract: A series current steering high speed analog-to-digital converter. The converter includes means for providing n number of weighted current sources and drains of having 1/2, 1/4, 1/8, - - - 1/2.sup.n of a reference current, I.sub.r, wherein n represents an integer number, n diodes bridge circuits connected in series, n comparators coupled to corresponding bridging arms of the bridge circuits. The current sources and drains, the bridge circuits and the comparators are operatively coupled to form n sections in series to steer the currents therethrough so that the first section compares the amplitude of the input current with 1/2 of the reference current and generates the most significant bit, the second section compares the absolute valve of the difference between the input current and the 1/2 to 1/4 of the reference current for generating the second most significant bit, and so on, till the n bit digital word output is formed from the input current.