Abstract: A dynamic-tile neural network accelerator allows for the number and size of computational tiles to be re-configured. Each sub-array of computational cells has edge cells on the left-most column that have an added vector mux that feeds the cell output back to an adder-comparator to allow Rectified Linear Unit (ReLU) and pooling operations that combine outputs shifted in from other cells. The edge cells drive external output registers and receive external weights. The weights and outputs are shifted in opposite directions horizontally between cells while control and input data are shifted in a same direction vertically between cells. A column of row data selectors is inserted between sub-arrays to bypass weights and output data around sub-arrays, while a row of column data selectors are inserted between sub-arrays to bypass control and input data. Larger tiles are configured by passing data directly through these selectors without bypassing.

Abstract: The invention relates to an improved process for providing purified styrenic monomers, such as styrene, from styrene-containing polymer waste. Styrene-containing waste is depolymerized in a suitable reactor, and the depolymerization products are condensed and separated in a three-step distillation process.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.

Abstract: The present invention is concerned with a novel freight container with improved characteristics. The container has a first portion and a second portion. The container is adapted to assume a first configuration in which the container has a maximum volume and a third configuration in which said container has a minimum volume. In the first configuration, the second portion is extended away from said first portion; side walls of said first and second portions are extending vertically in normal use; and at least some of said side walls are foldable. In the second configuration said side walls are folded in such a way to allow top walls of the first and second portions and bottom walls of the first and second portions be brought towards and adjacent each other whereby the minimum volume of the container is achieved.

Abstract: The present invention is concerned with a novel freight container with improved characteristics. The container has a first portion and a second portion. The container is adapted to assume a first configuration in which the container has a maximum volume and a third configuration in which said container has a minimum volume. In the first configuration, the second portion is extended away from said first portion; side walls of said first and second portions are extending vertically in normal use; and at least some of said side walls are foldable. In the second configuration said side walls are folded in such a way to allow top walls of the first and second portions and bottom walls of the first and second portions be brought towards and adjacent each other whereby the minimum volume of the container is achieved.

Abstract: The invention is based on the discovery of methods for purification of an acid active hyaluronidase found in human plasma (hpHAse), including both biochemical and immunoaffinity purification methods The method of immunoaffinity purification of the invention is based on the discovery of a method for identifying antibodies that specifically bind native hpHAse (anti-native hpHAse antibodies), and anti-native hpHAse antibodies identified by this screening method. The invention also features an assay for sensitive detection of HAse activity using biotinylated hyaluronic acid (bHA). Purification and characterization of hpHAse lead to the inventors' additional discovery that hpHAse is encoded by the LuCa-1 gene, which gene is present in the human chromosome at 3p21.3, a region associated with tumor suppression. The invention additionally features methods of treating tumor-bearing patients by administration of hpHAse and/or transformation of cells with hpHAse-encoding DNA.

Abstract: The invention provides a buffer device for a processing apparatus for semiconductor components. The apparatus comprises a transportation track for conveying semiconductor components between processing machines, and a transfer mechanism for transferring semiconductor components between the transportation track and a receiving section of a processing machine along a travelling path. The buffer device is operative to receive and store semiconductor components from the transfer mechanism.

Abstract: The invention provides a buffer device for a processing apparatus for semiconductor components. The apparatus comprises a transportation track for conveying semiconductor components between processing machines, and a transfer mechanism for transferring semiconductor components between the transportation track and a receiving section of a processing machine along a travelling path. The buffer device is operative to receive and store semiconductor components from the transfer mechanism.