Abstract: An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network. A preselected portion of the output of the bit transition counting network is combined with a preselected portion of the bits of the shift register network to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system under test. The fault detecting capability approaches 100 percent with an imbedded indication of the input test pattern duration as verification.

Abstract: An apparatus for testing circuit board systems utilizing microprocessors which includes means for selectively exercizing each terminal or pin of the board system during each step of the testing protocol. Each step of the protocol can be preselected to operate according to an automatic sequence or according to a preprogrammed manner, or the apparatus may be conditioned to receive a response from the circuit board system at a selected terminal during a selected step of the testing protocol. The testing apparatus further includes an interactive interface to permit the board system under test to control the speed and sequence of the test procedure. The testing apparatus is capable of exercizing the board systems under test in a simulated environment at typically normal operating speeds so that degradation of system performance related to operational speed and other factors found in an operating environment can be analyzed.