Patents by Inventor Tim Yee He
Tim Yee He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12353239Abstract: A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.Type: GrantFiled: June 23, 2023Date of Patent: July 8, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Tim Yee He, Siavash Fallahi, Zhi Chao Huang, Ali Nazemi, Jun Cao
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Publication number: 20240427371Abstract: A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.Type: ApplicationFiled: June 23, 2023Publication date: December 26, 2024Applicant: Avago Technologies International Sales Pte. LimitedInventors: Tim Yee He, Siavash Fallahi, Zhi Chao Huang, Ali Nazemi, Jun Cao
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Patent number: 12068748Abstract: A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.Type: GrantFiled: August 29, 2022Date of Patent: August 20, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Lakshmi Rao, Siavash Fallahi, Tim Yee He, Ali Nazemi, Jun Cao
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Publication number: 20240072770Abstract: A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Inventors: Lakshmi RAO, Siavash Fallahi, Tim Yee He, Ali Nazemi, Jun Cao
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Patent number: 10931288Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: GrantFiled: December 26, 2019Date of Patent: February 23, 2021Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
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Publication number: 20200304129Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: ApplicationFiled: December 26, 2019Publication date: September 24, 2020Inventors: Zhiyu RU, Tim Yee HE, Siavash FALLAHI, Ali NAZEMI, Delong CUI, Jun CAO
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Patent number: 10523220Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.Type: GrantFiled: March 18, 2019Date of Patent: December 31, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao