Abstract: An electromechanical system. The electromechanical system includes: a microelectromechanical (MEMS) apparatus which has a component which can oscillate; a signal processing apparatus which is designed to receive and process a signal output by the MEMS apparatus; a voltage provision apparatus which is designed to provide at least one supply voltage for the signal processing apparatus, wherein the voltage provision apparatus includes at least one switching regulator. The voltage provision apparatus can be operated in a synchronous operating state and in an asynchronous operating state.

Abstract: A system having a micromechanical clocking system component a clocking system component. The system includes a micromechanical oscillation element, which is able to be induced to an oscillation with a natural frequency, and a first circuit, which generates from the natural frequency of the oscillation element a clock frequency which is pre-calibrated to a predefined setpoint clock frequency; a memory for the remaining deviation of the clock frequency from the setpoint clock frequency, the deviation having been individually determined for the clocking system component; and a processing unit which generates a reference time basis for at least a part of the system on the basis of the generated clock frequency and the stored deviation.

Abstract: A micromechanical sensor, including a micromechanical chip having a first micromechanical structure, a first evaluation chip, having a first application-specific integrated circuit, and a second evaluation chip having a second application-specific integrated circuit. The first evaluation chip and the micromechanical chip are situated in a stacked manner, the micromechanical chip being directly electrically conductively connected with the first evaluation chip and the first evaluation chip being directly electrically conductively connected with the second evaluation chip. The first application-specific integrated circuit primarily includes analog circuit elements and the second application-specific circuit primarily includes digital circuit elements.

Abstract: A sensor-data processing device, including at least one interface to communicate with at least one sensor element for detecting sensor events; at least one interface to communicate with at least one external computer device for processing sensor data representing the sensor events; devices for generating at least one time base specific to the sensor-data processing device; a device for assigning time stamps to the sensor events, the time stamps being based on the time base of the sensor-data processing device and being specific to the sensor-data processing device; a device for receiving a request signal from the computer device; with the aid of the computer device, the request signal being able to be assigned a time stamp based on a time base specific to the computer device; and a device for assigning a time stamp specific to the sensor-data processing device, to the request signal.

Abstract: A system component, including an interface for a data bus, a defined communication protocol being used on the data bus which determines the data sequence of access requests for sending and receiving data. The data of an access request includes pieces of information about the access direction. The system component includes a register unit including data registers. The system component includes a processing unit for the data of an access request. The interface is optionally operable in a first or a second operating mode. In the first operating mode, the data of an access request is supplied to the register unit to identify a register address, so that the corresponding read or write access takes place on the identified data register. In the second mode, the data of an access request is supplied to the processing unit and the corresponding read or write access is handled by the processing unit.

Abstract: A micromechanical sensor, including a micromechanical chip having a first micromechanical structure, a first evaluation chip, having a first application-specific integrated circuit, and a second evaluation chip having a second application-specific integrated circuit. The first evaluation chip and the micromechanical chip are situated in a stacked manner, the micromechanical chip being directly electrically conductively connected with the first evaluation chip and the first evaluation chip being directly electrically conductively connected with the second evaluation chip. The first application-specific integrated circuit primarily includes analog circuit elements and the second application-specific circuit primarily includes digital circuit elements.

Abstract: A system having a micromechanical clocking system component a clocking system component. The system includes a micromechanical oscillation element, which is able to be induced to an oscillation with a natural frequency, and a first circuit, which generates from the natural frequency of the oscillation element a clock frequency which is pre-calibrated to a predefined setpoint clock frequency; a memory for the remaining deviation of the clock frequency from the setpoint clock frequency, the deviation having been individually determined for the clocking system component; and a processing unit which generates a reference time basis for at least a part of the system on the basis of the generated clock frequency and the stored deviation.

Abstract: A system component, including an interface for a data bus, a defined communication protocol being used on the data bus which determines the data sequence of access requests for sending and receiving data. The data of an access request includes pieces of information about the access direction. The system component includes a register unit including data registers. The system component includes a processing unit for the data of an access request. The interface is optionally operable in a first or a second operating mode. In the first operating mode, the data of an access request is supplied to the register unit to identify a register address, so that the corresponding read or write access takes place on the identified data register. In the second mode, the data of an access request is supplied to the processing unit and the corresponding read or write access is handled by the processing unit.

Abstract: A sensor-data processing device, including at least one interface to communicate with at least one sensor element for detecting sensor events; at least one interface to communicate with at least one external computer device for processing sensor data representing the sensor events; devices for generating at least one time base specific to the sensor-data processing device; a device for assigning time stamps to the sensor events, the time stamps being based on the time base of the sensor-data processing device and being specific to the sensor-data processing device; a device for receiving a request signal from the computer device; with the aid of the computer device, the request signal being able to be assigned a time stamp based on a time base specific to the computer device; and a device for assigning a time stamp specific to the sensor-data processing device, to the request signal.

Abstract: A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.

Abstract: A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an analog delay line nor a signal divider unit is to be provided between the digital ramp oscillator or discrete time oscillator and the digital-to-time converter, wherein less analog circuitry is susceptible for noise and for ground bounce in the digital environment, it is proposed to provide at least one phase measurement unit (10);—at least one loop filter unit (40; 40?) being provided with at least one output signal (delta-phi) of at least one phase detector unit (30); at least one digital ramp oscillator unit or discrete time oscillator unit (50; 50?) being provided with at least one output signal, in particular with at least one increment (inc), of the loop filter unit (40; 40?)

Abstract: The present invention provides for spread spectrum receiver (1) and related method arranged for the receipt and processing of a spread spectrum signal wherein a PRN code is generated locally as an intended replica of a received signal code and a correlation threshold test is conducted on the received signal to determine the state of suspected code acquisition. The baseband signal derived from the received signal is processed by the microprocessor (14) but the correlation threshold test is conducted remote from the microprocessor (14) and a received signal is then flagged for subsequent processing by the microprocessor (14) if the threshold value according to the correlation threshold test is exceeded.