Abstract: One embodiment relates to a feedback receiver (FBR). The FBR includes a FBR signal input configured to receive a radio frequency (RF) signal, a first local oscillator (LO) signal input configured to receive a first LO signal having an LO frequency, and a second LO signal input configured to receive a second LO signal having the LO frequency. The second LO signal is phase shifted by approximately 90° relative to the first LO signal. FBR also includes a divider that induces a time-varying phase shift in the first and second LO signals while concurrently retaining a 90° phase shift between the first and second LO signals.

Abstract: A signal processing device for providing first and second analog signals includes first and second clocked digital signal path circuits and a transit time difference measuring device. The first clocked digital signal path circuit is configured to yield first digital data for providing a first analog signal. The second clocked digital signal path circuit is configured to yield second digital data for providing the second analog signal. The transit time difference measuring device is configured to yield a transit time difference measuring signal describing a difference between a signal transit time along a first measuring path and a signal transit time along a second measuring path, with the first measuring path including a first clock supply allocated to the first clocked digital signal path circuit, and with the second measuring path including a second clock supply allocated to the second clocked digital signal path circuit.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: One embodiment of the present invention relates to an apparatus for preventing remodulation in a transmission chain. A first offset generation circuit selectively introduces a first frequency offset into in-phase (I) and quadrature phase (Q) equivalent baseband signals. A second offset generation circuit selectively introduces a second frequency offset into an oscillator output signal. The frequency of the offset oscillator output signal is divided by a divider to form offset local oscillator signals, which are provided to up-conversion mixers that modulate the offset equivalent baseband signals onto the offset local oscillator signals to generate a composite modulated output signal. The first and second frequency offsets are chosen to have values that cancel during modulation. However, because the second frequency offset shifts the offset oscillator output signal's frequency to a value that is no longer a harmonic of the composite modulated output signal's frequency, remodulation is prevented.

Abstract: A high-frequency switching assembly having a first switching state and a second switching state includes a transmitter and a switch assembly. The transmitter includes a primary side and a secondary side having a first secondary side terminal and a second secondary side terminal and is configured to transmit an HF input signal applied to its primary side to its secondary side by means of inductive coupling. The switch assembly is configured to apply, in one state, a first reference potential to the first secondary side terminal. Further, the switch assembly is implemented to apply, in another state, a second reference potential to the second secondary side terminal.

Abstract: The present disclosure relates to I/Q modulation circuits, devices, and methods.

Abstract: The present disclosure relates to I/Q modulation circuits, devices, and methods.

Abstract: A transmitter includes a transformer that is configured to transform a baseband signal into an amplitude information signal and a phase information signal. The transmitter includes a ramping control unit configured to generate a power control signal. The transmitter includes a mixer that is configured to combine the amplitude information signal with the power control signal and produce a second amplitude information signal. The transmitter includes a modulator that is configured to modulate the second amplitude information signal on the phase information signal and produce an output signal.

Abstract: A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a predetermined value during the transmission of the data word. A determination unit uses the number of clock cycles of the clock signal during which the enable signal is at the predetermined value to determine the digital interface standard on which the data word transmitted during these clock cycles is based.

Abstract: A signal processing device is provided that includes a modulation unit that produces an amplitude element as well as a phase element from components that are applied thereto. A correction device is also provided, in which at least one of the components is supplied and is compared with an ideal nominal value. This is used to produce a correction factor, which is multiplied by the component which has been compared with the nominal value. The correction factor determined is used to correct any offset or distortion of the components produced by analog circuits.

Abstract: A flip-flop circuit arrangement and an associated method are disclosed, wherein a changeover between a master and a slave block is not effected by switching on and switching off respective current sources, but rather by impressing a compensation current that effects the changeover. One or more aspects of the present invention make it possible to reduce a supply voltage and at the same time, on account of low parasitic capacitances of the circuit, to provide a frequency divider in the gigahertz range which can be integrated using MOS circuit technology.

Abstract: The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register connected thereto which is coupled to a serial bus. A control unit controls the transfer of test data to a selected function block on the basis of the state of a mode-of-operation memory cell in the respective test register. This means that there is little involvement required to put individual function blocks of a chip deliberately into a test mode and to program them as appropriate, while other function blocks are operating in normal mode. The principle described allows a high degree of flexibility with regard to the testing of integrated circuits with a multiplicity of functional assemblies.

Abstract: A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit. The delay circuit can be activated by a control signal at a control input and is designed for outputting a first signal after a first time period and for outputting a second signal after a time period after the outputting of the first signal. The reset generator circuit comprises a generator circuit designed for outputting a reset signal in the event of detection of the first signal up to the detection of the second signal. Furthermore, the reset generator circuit contains a comparison device designed for a comparison of a supply potential with a potential threshold value and for outputting the control signal in the event of the potential threshold value being exceeded. The delay circuit and the generator circuit can be controlled by the comparison device.

Abstract: An integrated semiconductor circuit has a tunable resistor circuit whose total resistance value can be altered, the total resistance value being stipulated by a digital control word. A comparator compares a first voltage applied to the tunable resistor circuit with a second voltage applied to an external resistor element. A trimmer is coupled to the comparator and to the resistor circuit and provides the digital control word for the tunable resistor circuit. The trimmer determines that digital control word for which the resistor circuit has a total resistance value at which the first voltage is in a prescribed ratio to the second voltage.

Abstract: A signal processing device is provided that includes a modulation unit that produces an amplitude element as well as a phase element from components that are applied thereto. A correction device is also provided, in which at least one of the components is supplied and is compared with an ideal nominal value. This is used to produce a correction factor, which is multiplied by the component which has been compared with the nominal value. The correction factor determined is used to correct any offset or distortion of the components produced by analog circuits.

Abstract: A transmitter includes a transformer that is configured to transform a baseband signal into an amplitude information signal and a phase information signal. The transmitter includes a ramping control unit configured to generate a power control signal. The transmitter includes a mixer that is configured to combine the amplitude information signal with the power control signal and produce a second amplitude information signal. The transmitter includes a modulator that is configured to modulate the second amplitude information signal on the phase information signal and produce an output signal.

Abstract: A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a predetermined value during the transmission of the data word. A determination unit uses the number of clock cycles of the clock signal during which the enable signal is at the predetermined value to determine the digital interface standard on which the data word transmitted during these clock cycles is based.

Abstract: The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register connected thereto which is coupled to a serial bus. A control unit controls the transfer of test data to a selected function block on the basis of the state of a mode-of-operation memory cell in the respective test register. This means that there is little involvement required to put individual function blocks of a chip deliberately into a test mode and to program them as appropriate, while other function blocks are operating in normal mode. The principle described allows a high degree of flexibility with regard to the testing of integrated circuits with a multiplicity of functional assemblies.

Abstract: A flip-flop circuit arrangement and an associated method are disclosed, wherein a changeover between a master and a slave block is not effected by switching on and switching off respective current sources, but rather by impressing a compensation current that effects the changeover. One or more aspects of the present invention make it possible to reduce a supply voltage and at the same time, on account of low parasitic capacitances of the circuit, to provide a frequency divider in the gigahertz range which can be integrated using MOS circuit technology.

Abstract: A reset generator circuit has an oscillator circuit and a delay circuit having a clock signal input, which is connected to an output of the oscillator circuit. The delay circuit can be activated by a control signal at a control input and is designed for outputting a first signal after a first time period and for outputting a second signal after a time period after the outputting of the first signal. The reset generator circuit comprises a generator circuit designed for outputting a reset signal in the event of detection of the first signal up to the detection of the second signal. Furthermore, the reset generator circuit contains a comparison device designed for a comparison of a supply potential with a potential threshold value and for outputting the control signal in the event of the potential threshold value being exceeded. The delay circuit and the generator circuit can be controlled by the comparison device.